From patchwork Sat Dec 15 03:01:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 153919 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp102255ljp; Fri, 14 Dec 2018 19:02:31 -0800 (PST) X-Google-Smtp-Source: AFSGD/XeJq9YV0AfNqRRHxNHzefQi+jLDTO4qkqOj+meX4zf4Mr+PQjkVDwaiwQ0nT4TkxCwiLWP X-Received: by 2002:a17:902:2a0a:: with SMTP id i10mr5029261plb.323.1544842951396; Fri, 14 Dec 2018 19:02:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544842951; cv=none; d=google.com; s=arc-20160816; b=rNWEY5Y128Jz9cqYnJG3j5ljs5orsqPOmBPyE8VTpiOZn7MWkARybjyRy1zwlRWrmr Wd7B5aPW209bPnZ20lufCg9cSFCAPXk/PuJLHRGGF6tE8qry+8+kzAj8aqqEomk5vHsV /VpcU6URk9Uu8XE/OSI16ZB65tYbR1qdDyFAv+UGjgTRAo9dMWqka4NJTastrsxcFHRn zPH16vBKSwMmJOLI30ciF8ArBbjHvDBRfs1MhMixBfiM3ZMwuAbHlTX1UyB///cIoBtv T76C4jGST2h2pJAriVqfUio8kCkZAZtj3R5emfB2FjudlYZ+HJtt/3UZov2ge9QTBh1M 8Crw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=1fNJLUvL39cWBNfpOmnxroSKUC/RnHz0oy8A/ibN2iA=; b=I2IFfjTkSxvGa6w+HdrvA5pxAKTrCJJXW5u6vgMt95xk12Ss2z3e7WkwEPOOSZEQ6f QK3/QJT3w0zhEfDzcg+I01AcsKvObdRjqzV7CPM6XfNkoKvmc1gQ3G4KXIZKHmzRzzM4 VIXOpm4xv6JlQlGYW6VjW0Ae7B6veyz197cVVI/BoW7ldZ2JNjSSRLWXwqtEq2FYAe3L 6RdniVZ+Khe/p5Pz5pMz7kYBk2hEoz6ECHmfg56zcjPtFUGH6OqQD3JKuXWAt6R6ocjX SxtW6VnQv+eGHdAMxMV5KJuplTI6m0wRNEAlfRl7oudNWBWDVqqZolRMScARQlS8Z0d6 Xzkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="hOMvtWf/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d1si5619786pgg.301.2018.12.14.19.02.31; Fri, 14 Dec 2018 19:02:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="hOMvtWf/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729859AbeLODC3 (ORCPT + 6 others); Fri, 14 Dec 2018 22:02:29 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:36666 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729837AbeLODC3 (ORCPT ); Fri, 14 Dec 2018 22:02:29 -0500 Received: by mail-pg1-f195.google.com with SMTP id n2so3528732pgm.3 for ; Fri, 14 Dec 2018 19:02:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1fNJLUvL39cWBNfpOmnxroSKUC/RnHz0oy8A/ibN2iA=; b=hOMvtWf/WTmzGChczsMxD9Tel3C3DE6XJwxivQdJu64SXdwKEZeKyt8j2YXpOLC+Cb vSIXBhKmmLSqZwf+dN0tcGfg1iZzs6Lz+f2iLCJ0f+4QLscjVv1oQq4J+ucTuMDZRj6n wTLKGPCKCzCRxdE4Ab1TcKKrjLuYlXfr1FZi4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1fNJLUvL39cWBNfpOmnxroSKUC/RnHz0oy8A/ibN2iA=; b=BOrGo7Dxv9dyEeMSWOSTGyywZbzg46CAbQfjt7/dBbOIwdzlXzxSh5E+5cmx4idNY+ CXSc5q/9xjHhrrMM2vJlKj4E2n1xsT9X9V7LFVPgVtAnbkd1GVJDG5kQQkAdMofnV7I3 XERbyOsMzqrn0jLnNkqnckbf8NCbM0vhjMQZ+dHEKdFfk7Iuy+Xgf1TLYa7o6belIeU4 UqR/ucMmB20C+5Bbn9jxtX+Bax9QCfjmUi0j+FZFYq+aecdFf21gFB3RgE+Gat4OPayb ZZ+S6pMWrbIBgoLGC90ZcGhTnV+7LUwjEwq0hQEpI69c+3bqq1kEvEA+9pXqNbgQNF32 NF2Q== X-Gm-Message-State: AA+aEWaDvAHMyXy/BpYFdUDk+cyFn7mfFwMJp7ug0FVoqoAMggZJTpWB uBCIhINSMmsUI7BZj49jwmU1 X-Received: by 2002:a62:56c7:: with SMTP id h68mr5435897pfj.134.1544842948269; Fri, 14 Dec 2018 19:02:28 -0800 (PST) Received: from localhost.localdomain ([2409:4072:6301:5419:f1e8:77a0:59f7:2cb5]) by smtp.gmail.com with ESMTPSA id h15sm7309534pgl.43.2018.12.14.19.02.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Dec 2018 19:02:27 -0800 (PST) From: Manivannan Sadhasivam To: dinguyen@kernel.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, amit.kucheria@linaro.org, yossi@novtech.com, nazik@novtech.com, Manivannan Sadhasivam Subject: [PATCH 2/2] ARM: dts: Add support for 96Boards Chameleon96 board Date: Sat, 15 Dec 2018 08:31:52 +0530 Message-Id: <20181215030152.4386-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181215030152.4386-1-manivannan.sadhasivam@linaro.org> References: <20181215030152.4386-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree support for 96Boards Chameleon96 board from Novtech, Inc. based on Altera CycloneV SoC FPGA. This board is one of the Consumer Edition boards of the 96Boards family and has the following key features: * SoC - Intel Cyclone V SoC FPGA * GPU - Graphics based on Intel Video Suite for FPGA * RAM - 512MB DDR3L * USB - 2x USB2.0 Host, 1x USB2.0 OTG * Wireless - Wifi, BT More information about this board can be found in 96Boards product page: https://www.96boards.org/product/chameleon96/ Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/socfpga_cyclone5_chameleon96.dts | 130 ++++++++++++++++++ 2 files changed, 131 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts -- 2.17.1 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..d6cf081ec325 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -897,6 +897,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ + socfpga_cyclone5_chameleon96.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ diff --git a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts new file mode 100644 index 000000000000..f6561766d83f --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for the Chameleon96 + * + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +#include + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Novetech Chameleon96"; + compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x20000000>; /* 512MB */ + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + leds { + compatible = "gpio-leds"; + + user_led1 { + label = "green:user1"; + gpios = <&porta 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "green:user2"; + gpios = <&porta 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "green:user3"; + gpios = <&porta 25 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + user_led4 { + label = "green:user4"; + gpios = <&portb 3 GPIO_ACTIVE_LOW>; + panic-indicator; + linux,default-trigger = "none"; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + /* On Low speed expansion */ + label = "LS-I2C0"; + status = "okay"; +}; + +&i2c1 { + /* On Low speed expansion */ + label = "LS-I2C1"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + /* On High speed expansion */ + label = "HS-I2C2"; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&spi0 { + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; +}; + +&spi1 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; +}; + +&uart0 { + /* On Low speed expansion */ + label = "LS-UART1"; + status = "okay"; +}; + +&uart1 { + /* On Low speed expansion */ + label = "LS-UART0"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +};