From patchwork Fri May 3 05:31:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 163289 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp218617ill; Thu, 2 May 2019 22:31:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqxeefZYS5A00NexKWc0FGjtpkR/gFKST5ag+9w9bGguTkWKx4/UihkpFTgcHw3HmTog7ezc X-Received: by 2002:a62:479b:: with SMTP id p27mr8724871pfi.111.1556861509886; Thu, 02 May 2019 22:31:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556861509; cv=none; d=google.com; s=arc-20160816; b=wMfIzlRBD42Kd5FuG2Pan1O40yPaRFR0p+/8Q3ncORrwuxuDzVkTxtjvcmeogG98ro WZS070OSElq+emMPXP/EUYyml/MiWG6FWV1kEvUhRRmFOYBkIcAo49UH0NYDU1RWoUhP 9CjzARRAj1YgN8q4trmCEzEzgmLqfny5zTYfKEytbZ+W4ijkyvABGNI/mYN+Gy7uw3lm gy++YH1rYHNYV6IYBIpPOQQ8oGhVrjua2RjvNEYi3j1CtC0ucdoYZ2p92V1bk4WH14JQ VpY/6rIq5pZw+fiBVr493e2sJ0FxsZaXB+st707+WKNfeHYrrSDYd9uw/ByCEyEMXp7m S8QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=o2KnYtWi5SLktJn2op8zkW2H4ncbiGRKRjw+VMEkUnU=; b=kbguCInQc6TU4kDuD5aFXqNsuUETcJot4siHMvpGCF0FFRCwjJTgCYW+g/p9swtPKE AOQjBLnV+PW59FDf0tsPuz0hoXFYl6xC1mtOSfObKruunLMsJYQq9lagQHw5IvJDqRtw VMjQtdmCXwprJkBRZx5giuADySJM2FqEO1lp0VRJPs9N2iSRK5Bf7XZlcAAAyGVnKxRs eP28Vmp+lsNhhSUpw1HuBYzK8XaxfzNMov/jkR+W94O/ZW/wp3E5I66H3nTg7em19tfT EM2dvHYBlPtwSfDFOtAbrgifY9SmNNWMFowt/jJUprq0aSCfP7RtwNmdPzUQWMtOmt0j 0bDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HMBjz4Vx; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a8si1293527ple.344.2019.05.02.22.31.49; Thu, 02 May 2019 22:31:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HMBjz4Vx; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726407AbfECFbt (ORCPT + 7 others); Fri, 3 May 2019 01:31:49 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:45332 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725793AbfECFbs (ORCPT ); Fri, 3 May 2019 01:31:48 -0400 Received: by mail-pg1-f193.google.com with SMTP id i21so2155626pgi.12 for ; Thu, 02 May 2019 22:31:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=o2KnYtWi5SLktJn2op8zkW2H4ncbiGRKRjw+VMEkUnU=; b=HMBjz4VxsRY0GQSmLRIjcd/LPfpLc9xSHhYK+CETWHZGNTwq8RwHcbROkiHwm+6Ghi EDy0OWzoxVBy78gHvt5bKH9BZYqXNeXa3khB1qmIh/wgfyptgf1NEurtoc+Y9Ey4uEsW HVOWDx7mFk+nhWnVsunMPSj+1aYqaVbeRyUloYlht+SgOoLtw3TSpsDEFOn1rdSh0mRN l7RUjBmSJ+Yg04dgR7S12gOyQzgSYKqHCTkXY0rL5w+3tvpAPh9yWZT8QVEJivWTJPee N1umIS//rg3Drebciyt+JRxHGe2eUrLIPVHz1ys0xSsXqm2TndPy1/gDWRybFpTVpCfl V8kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=o2KnYtWi5SLktJn2op8zkW2H4ncbiGRKRjw+VMEkUnU=; b=VwcZ89D0WQtMdHzO8VXu8xo/iiSaJ+U6Y0+7mouVNcQ4Oewl/beWFFotAmvh0m/SAi sUSqIu4DoJidqZjPAnGBmYM0rc2jnVKu+pmsJsD9YjF8lefHg/GfWZfbHBGyQI5vPvjs TlG9WaCOajkA2Pj+77ONgQ2DvHOc1tCF80DnYlX+LJu7fX2XFOiyJ9WQxa/u0iyCG67D GIoq5m0lXPG64ehD043sjRBLYv8eZCh/dN/J68UcItQZeBx4T9NEn5/fTN+eswrYBQoa IIWTr+Q+WgwkuP43jOHZbdqYWGjNHjeUpz2bCZAf7ev8+mISY494Pp6w0/v6oleMpYtQ pu+A== X-Gm-Message-State: APjAAAXaDpptnyzcdRGX+W0dtm+vp0TT0GY7xtLX8n/huEpE6lCfVZ/3 Ns7ePUMUdubsNgr4nJv1wdZS X-Received: by 2002:a63:6fc1:: with SMTP id k184mr8099288pgc.239.1556861508351; Thu, 02 May 2019 22:31:48 -0700 (PDT) Received: from localhost.localdomain ([2405:204:72c7:3835:31df:f367:f70b:ed86]) by smtp.gmail.com with ESMTPSA id l15sm1152226pgb.71.2019.05.02.22.31.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 May 2019 22:31:47 -0700 (PDT) From: Manivannan Sadhasivam To: mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, robh+dt@kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loic.pallardy@st.com, Manivannan Sadhasivam Subject: [PATCH 2/3] ARM: dts: stm32mp157: Add missing pinctrl definitions Date: Fri, 3 May 2019 11:01:22 +0530 Message-Id: <20190503053123.6828-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190503053123.6828-1-manivannan.sadhasivam@linaro.org> References: <20190503053123.6828-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing pinctrl definitions for STM32MP157 MPU. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 62 +++++++++++++++++++++++ 1 file changed, 62 insertions(+) -- 2.17.1 diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi index 85c417d9983b..0b5bcf6a7c97 100644 --- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi @@ -241,6 +241,23 @@ }; }; + i2c1_pins_b: i2c1-2 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_pins_sleep_b: i2c1-3 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + i2c2_pins_a: i2c2-0 { pins { pinmux = , /* I2C2_SCL */ @@ -258,6 +275,23 @@ }; }; + i2c2_pins_b: i2c2-2 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_pins_sleep_b: i2c2-3 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + i2c5_pins_a: i2c5-0 { pins { pinmux = , /* I2C5_SCL */ @@ -599,6 +633,34 @@ bias-disable; }; }; + + uart4_pins_b: uart4-1 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* UART4_RX */ + , /* UART4_CTS */ + ; /* UART4_RTS */ + bias-disable; + }; + }; }; pinctrl_z: pin-controller-z@54004000 {