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[209.132.180.67]) by mx.google.com with ESMTP id b74si9197210pfj.121.2019.05.10.11.45.57; Fri, 10 May 2019 11:45:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eSmkaRdf; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728042AbfEJSp4 (ORCPT + 7 others); Fri, 10 May 2019 14:45:56 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:40978 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727562AbfEJSp4 (ORCPT ); Fri, 10 May 2019 14:45:56 -0400 Received: by mail-pl1-f194.google.com with SMTP id f12so1204071plt.8 for ; Fri, 10 May 2019 11:45:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZM7SY/0BpFAbopYEDbwnieszVXK8F7PH873RQSPiOGw=; b=eSmkaRdfluc3LITMaj52pu9Lm3tSLmTqyzpSePda+Stm7E9Nvv4lCWt62yvZEMnqC3 r7afY22FHunRw47eNe4uw3BYf3x1JEdpF3RmPZ+Yp1CJG/T8fHghd/qMkCqdjmia/E3O EpojE9CCfBucSdWMnF3lhlPgGEUxGIdquEDFsKZJR/rjQ2TWYBca341e9eSShXJBow98 lJNweQrjhv+0lHoDhv9EjYUoC247BylKAH5g8Lfbwi6TycVeSCKXBH/1dIoV/GjQIhxa HrWmQa7dJDlgFxXV3fRkcBE4NtxIEYQ2u4trrqqeppiKG11BHlVV1p55O3CF0pE9+BJg pguQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZM7SY/0BpFAbopYEDbwnieszVXK8F7PH873RQSPiOGw=; b=VlB14h3go7+GRav0BVgMOqOAX34uXaCfLaoEwUm7UvMOH6y5RVSi9RX/hY+hQPo6ty 6XY426WSF/1BCGm3lrZf3tzyUXEh5J0parFaQfqskISnjhrlkqQKdQLFckaVYBSOpBPn PKnWNtTDrVNU1FgKxw/RpX3qItS1H76IM3Rj9ofcBZv6M7uoUlHL+8rh1ziTL95z7ksk 0ttVc/oV45MYLfGcomrbzDqQBArlJLEOa6dyQEL09OMRSgGSRORcy6mQN2e6qMjlsNC0 L+DuT9c7FpLLNj0qykRwHam5CpN01GP1KWNM4AI2+t5vbriv0bwbjEs/UGKT+LA9ibyF 8b7Q== X-Gm-Message-State: APjAAAW49wjEFdw1PWRBxTTZjUdWSYR6GRHHsqMiGRCcWiLjHrmWLBkO eT2fw6M60XxVfBTSpHq3nIPn X-Received: by 2002:a17:902:868e:: with SMTP id g14mr15465190plo.183.1557513955941; Fri, 10 May 2019 11:45:55 -0700 (PDT) Received: from localhost.localdomain ([2405:204:73c1:9991:95b6:5055:2390:bf9b]) by smtp.gmail.com with ESMTPSA id g188sm8652049pfc.151.2019.05.10.11.45.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 May 2019 11:45:54 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, robh+dt@kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH v3 2/4] arm64: dts: bitmain: Add reset controller support for BM1880 SoC Date: Sat, 11 May 2019 00:15:23 +0530 Message-Id: <20190510184525.13568-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190510184525.13568-1-manivannan.sadhasivam@linaro.org> References: <20190510184525.13568-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add reset controller support for Bitmain BM1880 SoC. This commit also adds reset support to UART peripherals. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Philipp Zabel --- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index fdfdc65d29ef..3ab039029bf2 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -5,6 +5,7 @@ */ #include +#include / { compatible = "bitmain,bm1880"; @@ -92,6 +93,12 @@ compatible = "bitmain,bm1880-pinctrl"; reg = <0x50 0x4B0>; }; + + rst: reset-controller@c00 { + compatible = "bitmain,bm1880-reset"; + reg = <0xc00 0x8>; + #reset-cells = <1>; + }; }; uart0: serial@58018000 { @@ -100,6 +107,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst BM1880_RST_UART0_1_CLK>; status = "disabled"; }; @@ -109,6 +117,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst BM1880_RST_UART0_1_ACLK>; status = "disabled"; }; @@ -118,6 +127,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst BM1880_RST_UART2_3_CLK>; status = "disabled"; }; @@ -127,6 +137,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst BM1880_RST_UART2_3_ACLK>; status = "disabled"; }; };