From patchwork Thu Jul 25 00:10:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 169653 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp10886759ilk; Wed, 24 Jul 2019 17:10:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqwuOKK2357LMAy8WgIF1bQADddOqj8VMTsF3VuJ5965szBcXshVvp4TobR3Vk0ESZjonjKr X-Received: by 2002:aa7:96a4:: with SMTP id g4mr14358197pfk.193.1564013433504; Wed, 24 Jul 2019 17:10:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564013433; cv=none; d=google.com; s=arc-20160816; b=mEEKtVKhhbVw53y4XVrBZDhZ+GXUWGfWC2zhobV/B2CK6O/dcvUDJxoNI3zby2/DZ1 q4To56/HufqTGdr0hqXdIYYk1yNKsuSBwiOAuWQl3snWKvUt29poqtN4trTGJt+zUXHI 3Xh3TSTQPY5SJMwVMlVNw+0CZoraEfr9BDT8vmF2M5yW66/jYpqQpX+fVY6lCQOSVdNv vUFDPYHLruHFh5rIIDw1bUM3hUhOGeNTs4mhlM8JdoSGLvJSBdsXC0XNGxC5vz28Qnem O7pwRRNRULZacHaHFMKr6s63BZlaNekqI3xL6zeZe5F9Jk/Hl9akHqdVFyIFTxW8N/MI dRYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4z/E3hbL6kFOSFGTSsBGYnS1r1u1XNf8C23axJEsGsU=; b=HKL8kIVRhKNmkWFH4rI4J9THmiNH3s86SRy2YkRc2VAyESyY7daeApPYM+BDTdBPJf IojUiWVbUqKHaXJ/SH1RQLRIkW/yekoqvZRwP/4xKLFqBbXA7YKXbyPlvp8Q+4clzg9N K4pMqQ5FeXK7HT4gKEksWzvgBZpApvpjVWq9uukiKxkPXCD6/brEZWgzku3r3h+fRB4v c8F4UmnFdmkhw26SpoB3jjWkD6daHegchgsqgEfqKCNrX7n4YLH7U+uFtx448eCHFxax Y2/8pveVk2U9FkQ+FENDU1wxCxprIXXkLIi24q/m1ldwJUmvc2v7YaFtERpGsgPAvjIw OXpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SNmAeI8i; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w6si16163393pjr.100.2019.07.24.17.10.33; Wed, 24 Jul 2019 17:10:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SNmAeI8i; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388057AbfGYAKc (ORCPT + 8 others); Wed, 24 Jul 2019 20:10:32 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:49502 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388323AbfGYAKc (ORCPT ); Wed, 24 Jul 2019 20:10:32 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x6P0ASu3015366; Wed, 24 Jul 2019 19:10:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1564013428; bh=4z/E3hbL6kFOSFGTSsBGYnS1r1u1XNf8C23axJEsGsU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SNmAeI8iNAJFdmjeXCzA4xwtq1noHDZNdgWvFsRblfl2IyMN/JENFWA5Re7380qw3 ekXF7RSyBTyS+2E5yTHnadnsvN19APl1Np4Y8kfatABHjaJGKUOu2Nxxx+Hn0TETKW SaDPLCO6+uEPEYVRV3wUimcDnRhrq8dX6AkTX31E= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x6P0ASb7026469 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 24 Jul 2019 19:10:28 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 24 Jul 2019 19:10:28 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 24 Jul 2019 19:10:28 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6P0ASiW107964; Wed, 24 Jul 2019 19:10:28 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6P0ASZ03267; Wed, 24 Jul 2019 19:10:28 -0500 (CDT) From: Suman Anna To: Tero Kristo , Nishanth Menon CC: , , Suman Anna Subject: [PATCH v2 1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes Date: Wed, 24 Jul 2019 19:10:17 -0500 Message-ID: <20190725001020.23781-2-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190725001020.23781-1-s-anna@ti.com> References: <20190725001020.23781-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AM65x Main NavSS block contains a Mailbox IP instance with multiple clusters. Each cluster is equivalent to an Mailbox IP instance on OMAP platforms. Add all the Mailbox clusters as their own nodes under the MAIN NavSS cbass_main_navss interconnect node instead of creating an almost empty parent node for the new K3 mailbox IP and the clusters as its child nodes. All these nodes are enabled by default in the base dtsi file, but any cluster that does not define any child sub-mailbox nodes should be disabled in the corresponding board dts files. NOTE: The NavSS only has a limited number of interrupts, so none of the interrupts generated by a Mailbox IP are added by default. Only the needed interrupts that are targeted towards the A53 GIC will have to be added later on in the board dts files alongside the corresponding sub-mailbox child nodes. Signed-off-by: Suman Anna --- v2: - Add interrupt-parent property and enable all clusters by default - Patch description revised accordingly v1: https://patchwork.kernel.org/patch/11053403/ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++ 1 file changed, 108 insertions(+) -- 2.22.0 diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 8413e80f9d3a..24c66f09e899 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -419,6 +419,114 @@ reg = <0x00 0x30e00000 0x00 0x1000>; #hwlock-cells = <1>; }; + + mailbox0_cluster0: mailbox@31f80000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f80000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; + + mailbox0_cluster1: mailbox@31f81000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f81000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; + + mailbox0_cluster2: mailbox@31f82000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f82000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; + + mailbox0_cluster3: mailbox@31f83000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f83000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; + + mailbox0_cluster4: mailbox@31f84000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f84000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; + + mailbox0_cluster5: mailbox@31f85000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f85000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; + + mailbox0_cluster6: mailbox@31f86000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f86000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; + + mailbox0_cluster7: mailbox@31f87000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f87000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; + + mailbox0_cluster8: mailbox@31f88000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f88000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; + + mailbox0_cluster9: mailbox@31f89000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f89000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; + + mailbox0_cluster10: mailbox@31f8a000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8a000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; + + mailbox0_cluster11: mailbox@31f8b000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8b000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + }; }; main_gpio0: main_gpio0@600000 {