From patchwork Wed Oct 23 10:13:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 177260 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp503212ill; Wed, 23 Oct 2019 03:14:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqwoxjFqwV03z4eNiS2pDLGkL1y+pZzu4knu8/LLvX5ZOlmZrXOLQn9eja2LtuOdcSu3mNlS X-Received: by 2002:a17:906:fcd4:: with SMTP id qx20mr32602707ejb.257.1571825645561; Wed, 23 Oct 2019 03:14:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571825645; cv=none; d=google.com; s=arc-20160816; b=HH8xNCghFLItp/ZUPn4eHuJbFQF6Vr31JvsDJQSy6sVt9lIA5TRree3B4kETX86KO4 C8vNF7r5cmCut8kfZbAxL0VxiLEWGVgwEC8XktdPL1jyUbrUMArs1fft8nFVH9aMz3J6 qQJx7TMhTY0DX0z0lMCSvzDpEvrCKlYekG9rqh/draja6X3NQ13HKGHB5w0OAbkpJ+dU /2a5+QDQ7mX+k14uOPoJHRsPLsW+DoLoULvYaa/IPPLzsTcSHYHEYcbB2Ju5wvhO0ZI/ Gnp1Zog9jRcemc8m8xWFGX7+74Kuxm2Dq+T3BpC6PGTNgtOeQMtxjddgdq0tQm7kDG77 grDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=/8I1+Cvz6IbFeheiaSsVn7Cwq7n7VSPCGObULiPr+0o=; b=R9ubYsQ3uFxFfNwWueMUbH7UQcf0hYdRTFuJ/MkbvrM0up1s2LJUMZztaa2hBhf+ot uQsK9cqBEDwBgnheh53j+YuF0nJbWD9vp9EOxk8lZQ9JQNsvN9nRscCddlP6sKHatTZg OWSrOICEBTiHdTY2j7gP21FPim6zEmD9TbvDpGqd08DdtE6TYbnlG5knkvLVvGch5hPa d183lAEhhWScXgNaNZh6CZfS95YhgQi2maL1oMpCBqmmNTDUXyNIrBsJsbadWnJ72ZLV 9ro+clXiqRiZmBkUmDFToa3TkHA9j/LFifh4SqCttCqgl1vnXBBUxgnOLCKFdPKJ5grG UKPg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id sd13si12302963ejb.256.2019.10.23.03.14.05; Wed, 23 Oct 2019 03:14:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404326AbfJWKOB (ORCPT + 8 others); Wed, 23 Oct 2019 06:14:01 -0400 Received: from mx2.suse.de ([195.135.220.15]:53858 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2404161AbfJWKNd (ORCPT ); Wed, 23 Oct 2019 06:13:33 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 85CCDB638; Wed, 23 Oct 2019 10:13:31 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v2 09/11] ARM: dts: rtd1195: Add UART resets Date: Wed, 23 Oct 2019 12:13:15 +0200 Message-Id: <20191023101317.26656-10-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191023101317.26656-1-afaerber@suse.de> References: <20191023101317.26656-1-afaerber@suse.de> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Associate the UART nodes with the corresponding reset controller bits. Signed-off-by: Andreas Färber --- v2: New arch/arm/boot/dts/rtd1195.dtsi | 2 ++ 1 file changed, 2 insertions(+) -- 2.16.4 diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi index fdcaf48a26f2..e2cdcbcf70f4 100644 --- a/arch/arm/boot/dts/rtd1195.dtsi +++ b/arch/arm/boot/dts/rtd1195.dtsi @@ -128,6 +128,7 @@ reg = <0x18007800 0x400>; reg-shift = <2>; reg-io-width = <4>; + resets = <&iso_reset 8>; clock-frequency = <27000000>; status = "disabled"; }; @@ -137,6 +138,7 @@ reg = <0x1801b200 0x100>; reg-shift = <2>; reg-io-width = <4>; + resets = <&reset2 28>; clock-frequency = <27000000>; status = "disabled"; };