From patchwork Tue Feb 25 09:40:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 204268 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C8C8C35DF5 for ; Tue, 25 Feb 2020 09:41:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2E9B424656 for ; Tue, 25 Feb 2020 09:41:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="teZkIihn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730036AbgBYJlX (ORCPT ); Tue, 25 Feb 2020 04:41:23 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:58960 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729813AbgBYJlX (ORCPT ); Tue, 25 Feb 2020 04:41:23 -0500 X-UUID: 721e411a3cc64084a78ff3760d139737-20200225 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=+9UHoIzAdnK80c9BwL+nHRfyx1ClCc92Z6SatpYKDaQ=; b=teZkIihnvPFB9jPlSPdL3kEank0tpg+L3SYNHhbJ6HWme6ps1I8sufj3HqU3bUk8AsbHLL78YqrIlb9vGh4fTj+l+P8yd1FcT0dZvSg3ka7s1R6UUwIBgHW/soQixexPqjEBQ93ZjSgfPrH9TqlKdsvmaw1RoyiYAURgz07ysFQ=; X-UUID: 721e411a3cc64084a78ff3760d139737-20200225 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1644798728; Tue, 25 Feb 2020 17:41:07 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 25 Feb 2020 17:39:45 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 25 Feb 2020 17:39:45 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , , , Jitao Shi Subject: [PATCH v8 1/7] dt-bindings: media: add pclk-sample dual edge property Date: Tue, 25 Feb 2020 17:40:51 +0800 Message-ID: <20200225094057.120144-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200225094057.120144-1-jitao.shi@mediatek.com> References: <20200225094057.120144-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: CDB7FC69F9E163707809811DAF93E1FF2E6374A0B1821E44F670BB6E4DC42DE72000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some chips's sample mode are rising, falling and dual edge (both falling and rising edge). Extern the pclk-sample property to support dual edge. Signed-off-by: Jitao Shi --- Documentation/devicetree/bindings/media/video-interfaces.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.21.0 diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt index f884ada0bffc..da9ad24935db 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.txt +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt @@ -118,8 +118,8 @@ Optional endpoint properties - data-enable-active: similar to HSYNC and VSYNC, specifies the data enable signal polarity. - field-even-active: field signal level during the even field data transmission. -- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock - signal. +- pclk-sample: sample data on rising (1), falling (0) or both rising and + falling (2) edge of the pixel clock signal. - sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively. - data-lanes: an array of physical data lane indexes. Position of an entry