From patchwork Fri Feb 28 08:14:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 204071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD7AAC3F2CF for ; Fri, 28 Feb 2020 08:16:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A699F246A3 for ; Fri, 28 Feb 2020 08:16:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="hzwrL3gW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726277AbgB1IQi (ORCPT ); Fri, 28 Feb 2020 03:16:38 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:44197 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725970AbgB1IQi (ORCPT ); Fri, 28 Feb 2020 03:16:38 -0500 X-UUID: 5d8339b037044464ab02b993a25ebc91-20200228 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qq+KUcgzlVGWns29Btx51jzjUGTyJT4I7+iIRw7EHiM=; b=hzwrL3gWGsbPTQ07YJbtv2cRFz6f9Fb/fJ73U+XFvJDFEJIBHA/mxuF0GPJ9YTctrcMu2CljLlMyZnMLaD8tjpCo5/JZ5T3EkHY8/wtsnw36tIE2o1hxxQKZfheJY22lF18Y2B34HePPEfjzvKu0VEscQ7kW91syOiG7HtRzPvU=; X-UUID: 5d8339b037044464ab02b993a25ebc91-20200228 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 505427480; Fri, 28 Feb 2020 16:15:37 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33DR.mediatek.inc (172.27.6.106) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 28 Feb 2020 16:11:25 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 28 Feb 2020 16:15:55 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , , , Jitao Shi Subject: [PATCH v11 4/6] dt-bindings: display: mediatek: convert the document format from txt to yaml Date: Fri, 28 Feb 2020 16:14:39 +0800 Message-ID: <20200228081441.88179-5-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200228081441.88179-1-jitao.shi@mediatek.com> References: <20200228081441.88179-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: D5D880BEAF2EA97033EFDF564F621931AD511FAB4539A61A11085AFE1BCBE93A2000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Jitao Shi --- .../display/mediatek/mediatek,dpi.txt | 45 -------- .../display/mediatek/mediatek,dpi.yaml | 100 ++++++++++++++++++ 2 files changed, 100 insertions(+), 45 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml -- 2.21.0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt deleted file mode 100644 index 4eeead1d39db..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt +++ /dev/null @@ -1,45 +0,0 @@ -Mediatek DPI Device -=================== - -The Mediatek DPI function block is a sink of the display subsystem and -provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel -output bus. - -Required properties: -- compatible: "mediatek,-dpi" - the supported chips are mt2701 , mt8173 and mt8183. -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "pixel", "engine", and "pll" -- port: Output port node with endpoint definitions as described in - Documentation/devicetree/bindings/graph.txt. This port should be connected - to the input port of an attached HDMI or LVDS encoder chip. - -Optional properties: -- pinctrl-names: Contain "gpiomode" and "dpimode". - pinctrl-names see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt -- pclk-sample: refer Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - -dpi0: dpi@1401d000 { - compatible = "mediatek,mt8173-dpi"; - reg = <0 0x1401d000 0 0x1000>; - interrupts = ; - clocks = <&mmsys CLK_MM_DPI_PIXEL>, - <&mmsys CLK_MM_DPI_ENGINE>, - <&apmixedsys CLK_APMIXED_TVDPLL>; - clock-names = "pixel", "engine", "pll"; - pinctrl-names = "active", "idle"; - pinctrl-0 = <&dpi_pin_func>; - pinctrl-1 = <&dpi_pin_idle>; - - port { - dpi0_out: endpoint { - pclk-sample = <0>; - remote-endpoint = <&hdmi0_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml new file mode 100644 index 000000000000..9878e9f2b12e --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek,dpi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: mediatek DPI Controller Device Tree Bindings + +maintainers: + - CK Hu + - Rob Herring + - Mark Rutland + +description: | + The Mediatek DPI function block is a sink of the display subsystem and + provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel + output bus. + +properties: + compatible: + enum: + - mediatek,mt2701-dpi + - mediatek,mt8173-dpi + - mediatek,mt8183-dpi + + reg: + maxItems: 1 + description: Physical base address and length of the controller's registers + + interrupts: + maxItems: 1 + description: The interrupt signal from the function block. + + clocks: + minItems: 3 + maxItems: 3 + items: + - description: Pixel Clock + - description: Engine Clock + - description: DPI PLL + + clock-names: + items: + - const: pixel + - const: engine + - const: pll + + pinctrl-names: + description: pinctrl-names refe Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + minItems: 2 + maxItems: 2 + items: + - const: active + - const: idle + + port: + type: object + description: + Output port node with endpoint definitions as described in + Documentation/devicetree/bindings/graph.txt. This port should be connected + to the input port of an attached HDMI or LVDS encoder chip. + + pclk-sample: + description: refer Documentation/devicetree/bindings/media/video-interfaces.txt. + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - port + +additionalProperties: false + +examples: + - | + dpi0: dpi@1401d000 { + compatible = "mediatek,mt8173-dpi"; + reg = <0 0x1401d000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DPI_PIXEL>, + <&mmsys CLK_MM_DPI_ENGINE>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + pinctrl-names = "active", "idle"; + pinctrl-0 = <&dpi_pin_func>; + pinctrl-1 = <&dpi_pin_idle>; + + port { + reg = <0>; + dpi0_out: endpoint { + pclk-sample = <0>; + remote-endpoint = <&hdmi0_in>; + }; + }; + }; + +...