From patchwork Wed Mar 11 07:40:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 203524 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDB73C10F25 for ; Wed, 11 Mar 2020 07:41:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B15E8222C3 for ; Wed, 11 Mar 2020 07:41:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IMTp8gc4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728469AbgCKHlI (ORCPT ); Wed, 11 Mar 2020 03:41:08 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:18327 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726198AbgCKHlH (ORCPT ); Wed, 11 Mar 2020 03:41:07 -0400 X-UUID: 769b7011e41e4c89b8b4c4ba5257be87-20200311 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=LkxTQ6EkbNDavsaknDTmCujK6P6DkEqHOkdqLklErpk=; b=IMTp8gc4JdjYowh4XonGi1wqO7V2sF2CqlOdBQDVULX0o+sh7jPnzTigiIuJ3aJ6BHW/L7MhwDplLFq96QoEmBwIUM4oO5/WJB+YYliE0o5bHpSeeOSILZJZOGlrhuNPWotm1koB2MScXHPT8FJuijA24MGzW4LfMY2SGC+ho00=; X-UUID: 769b7011e41e4c89b8b4c4ba5257be87-20200311 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1845059689; Wed, 11 Mar 2020 15:40:51 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 11 Mar 2020 15:38:24 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 11 Mar 2020 15:42:01 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , , , Jitao Shi Subject: [PATCH v3 1/4] dt-bindings: display: mediatek: add property to control mipi tx drive current Date: Wed, 11 Mar 2020 15:40:29 +0800 Message-ID: <20200311074032.119481-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200311074032.119481-1-jitao.shi@mediatek.com> References: <20200311074032.119481-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 722E361D831C8C3966132F721EB94F410BBC341B3127202F294AB6C020A316202000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a property to control mipi tx drive current: "drive-strength-microamp" Signed-off-by: Jitao Shi --- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.21.0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index a19a6cc375ed..d501f9ff4b1f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -33,6 +33,9 @@ Required properties: - #clock-cells: must be <0>; - #phy-cells: must be <0>. +Optional properties: +- drive-strength-microamp: adjust driving current, should be 1 ~ 0xF + Example: mipi_tx0: mipi-dphy@10215000 { @@ -42,6 +45,7 @@ mipi_tx0: mipi-dphy@10215000 { clock-output-names = "mipi_tx0_pll"; #clock-cells = <0>; #phy-cells = <0>; + drive-strength-microamp = <0x8>; }; dsi0: dsi@1401b000 {