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[79.52.251.133]) by smtp.googlemail.com with ESMTPSA id o27sm517717ejc.23.2020.04.03.16.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2020 16:26:09 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Bjorn Andersson , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/2] devicetree: bindings: phy: Document ipq806x dwc3 qcom phy Date: Sat, 4 Apr 2020 01:25:57 +0200 Message-Id: <20200403232559.25716-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200403232559.25716-1-ansuelsmth@gmail.com> References: <20200403232559.25716-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document dwc3 qcom phy hs and ss phy bindings needed to correctly inizialize and use usb on ipq806x SoC. Signed-off-by: Ansuel Smith --- .../bindings/phy/qcom,ipq806x-usb-phy-hs.yaml | 66 ++++++++++++++++ .../bindings/phy/qcom,ipq806x-usb-phy-ss.yaml | 78 +++++++++++++++++++ 2 files changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml new file mode 100644 index 000000000000..c1d690ce646b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER + +maintainers: + - Ansuel Smith + +description: + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer + controllers used in ipq806x. Each DWC3 PHY controller should have its + own node. + +properties: + compatible: + const: qcom,ipq806x-usb-phy-hs + + "#phy-cells": + const: 0 + + regmap: + maxItems: 1 + description: phandle to usb3 dts definition + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + description: | + - "ref" Is required + - "xo" Optional external reference clock + items: + - const: ref + - const: xo + +required: + - compatible + - "#phy-cells" + - regmap + - clocks + - clock-names + +examples: + - | + #include + + hs_phy_0: hs_phy_0 { + compatible = "qcom,ipq806x-usb-phy-hs"; + regmap = <&usb3_0>; + clocks = <&gcc USB30_0_UTMI_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + }; + + usb3_0: usb3@110f8800 { + compatible = "qcom,dwc3", "syscon"; + reg = <0x110f8800 0x8000>; + + /* ... */ + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml new file mode 100644 index 000000000000..53a07b35c3e9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER + +maintainers: + - Ansuel Smith + +description: + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer + controllers used in ipq806x. Each DWC3 PHY controller should have its + own node. + +properties: + compatible: + const: qcom,ipq806x-usb-phy-ss + + "#phy-cells": + const: 0 + + regmap: + maxItems: 1 + description: phandle to usb3 dts definition + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + description: | + - "ref" Is required + - "xo" Optional external reference clock + items: + - const: ref + - const: xo + + rx_eq: + maxItems: 1 + description: Override value for rx_eq. Default is 4. + + tx_deamp_3_5db: + maxItems: 1 + description: Override value for transmit preemphasis. Default is 23. + + mpll: + maxItems: 1 + description: Override value for mpll. Default is 0. + +required: + - compatible + - "#phy-cells" + - regmap + - clocks + - clock-names + +examples: + - | + #include + + ss_phy_0: ss_phy_0 { + compatible = "qcom,ipq806x-usb-phy-ss"; + regmap = <&usb3_0>; + clocks = <&gcc USB30_0_MASTER_CLK>; + clock-names = "ref"; + #phy-cells = <0>; + }; + + usb3_0: usb3@110f8800 { + compatible = "qcom,dwc3", "syscon"; + reg = <0x110f8800 0x8000>; + + /* ... */ + };