From patchwork Wed Apr 22 14:24:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 201626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E305C5518F for ; Wed, 22 Apr 2020 14:26:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4072C20CC7 for ; Wed, 22 Apr 2020 14:26:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="p78a3N7V" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727997AbgDVO0l (ORCPT ); Wed, 22 Apr 2020 10:26:41 -0400 Received: from vultr.net.flygoat.com ([149.28.68.211]:59336 "EHLO vultr.net.flygoat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727933AbgDVO0l (ORCPT ); Wed, 22 Apr 2020 10:26:41 -0400 Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id 1287820CD7; Wed, 22 Apr 2020 14:26:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1587565589; bh=p5gnRIZ0/bXq2CwVeK3wJszOYSy/wquMYCbBmYV8dBU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p78a3N7VO3xp7N0BySi1ZbKQiCW0BH819CFCjPTso4wJbaMgdXdGrhXgdl9/A3ixZ 0IUAHGI9PLpK6bpRgxl3ZlfWWUNphp9h8dYsfMCGh6D0yd90OBws1+F7JVkEBAUNR6 7w2kiRjOhk4sl0VD0qHuzaeS6hYtE9AcfMXeYg8YCOYWVp4lAa7H7ZP5062uB/qVZR 7+NJsYEIddLiPz+dmOYT0cSz/6D9EJei7TJD3LREeqVMqDVNIFAD91W/gBguDJDaH8 GAZi9VdrV00DxNthO9e7ShlernKT+pAezi3zG60HiJyjSlPaAcimR4/GZcT6qkyxiD PN8Ws/TpyT5ww== From: Jiaxun Yang To: linux-mips@vger.kernel.org, maz@kernel.org Cc: Jiaxun Yang , Thomas Gleixner , Jason Cooper , Rob Herring , Huacai Chen , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 6/6] dt-bindings: interrupt-controller: Add Loongson PCH MSI Date: Wed, 22 Apr 2020 22:24:26 +0800 Message-Id: <20200422142428.1249684-7-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200422142428.1249684-1-jiaxun.yang@flygoat.com> References: <20200422142428.1249684-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for Loongson PCH MSI controller. Signed-off-by: Jiaxun Yang --- .../loongson,pch-msi.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml new file mode 100644 index 000000000000..dfb9cecacba0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson PCH MSI Controller + +maintainers: + - Jiaxun Yang + +description: | + This interrupt controller is found in the Loongson-7A family of PCH for + transforming interrupts from PCIe MSI into HyperTransport vectorized + interrupts. + +properties: + compatible: + const: loongson,pch-msi-1.0 + + reg: + maxItems: 1 + + loongson,msi-base-vec: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + u32 value of the base of parent HyperTransport vector allocated + to PCH MSI. + + loongson,msi-num-vecs: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + u32 value of the number of parent HyperTransport vectors allocated + to PCH MSI. + + msi-controller: true + +required: + - compatible + - reg + - msi-controller + - loongson,msi-base-vec + - loongson,msi-num-vecs + +examples: + - | + #include + msi: msi-controller@2ff00000 { + compatible = "loongson,pch-msi-1.0"; + reg = <0x2ff00000 0x4>; + msi-controller; + loongson,msi-base-vec = <64>; + loongson,msi-num-vecs = <64>; + interrupt-parent = <&htvec>; + }; +...