From patchwork Tue May 26 14:40:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 200030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6F63C433E5 for ; Tue, 26 May 2020 14:42:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 86B1C208C9 for ; Tue, 26 May 2020 14:42:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728942AbgEZOmo (ORCPT ); Tue, 26 May 2020 10:42:44 -0400 Received: from out28-148.mail.aliyun.com ([115.124.28.148]:34689 "EHLO out28-148.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726437AbgEZOmo (ORCPT ); Tue, 26 May 2020 10:42:44 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.0750449|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.65544-0.000441388-0.344119; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03300; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=11; RT=11; SR=0; TI=SMTPD_---.Hdvl59T_1590504067; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.Hdvl59T_1590504067) by smtp.aliyun-inc.com(10.147.41.143); Tue, 26 May 2020 22:42:37 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, sernia.zhou@foxmail.com, zhenwenjin@gmail.com, paul@crapouillou.net Subject: [PATCH v10 1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers. Date: Tue, 26 May 2020 22:40:39 +0800 Message-Id: <20200526144044.71413-3-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20200526144044.71413-1-zhouyanjie@wanyeetech.com> References: <20200526144044.71413-1-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It is not necessary to use spinlock when reading registers, so remove it from cgu.c. Suggested-by: Paul Cercueil Suggested-by: Paul Burton Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Paul Cercueil --- Notes: v2: New patch. v2->v3: Adjust order from [5/5] in v2 to [1/5] in v3. v3->v4: Remove the spinlock around ingenic_cgu_gate_get(). v4->v5: Rebase on top of kernel 5.6-rc1. v5->v6: No change. v6->v7: No change. v7->v8: No change. v8->v9: No change. v9->v10: No change. drivers/clk/ingenic/cgu.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 6e963031cd87..ab1302ad1450 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -76,16 +76,13 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) const struct ingenic_cgu_pll_info *pll_info; unsigned m, n, od_enc, od; bool bypass; - unsigned long flags; u32 ctl; clk_info = &cgu->clock_info[ingenic_clk->idx]; BUG_ON(clk_info->type != CGU_CLK_PLL); pll_info = &clk_info->pll; - spin_lock_irqsave(&cgu->lock, flags); ctl = readl(cgu->base + pll_info->reg); - spin_unlock_irqrestore(&cgu->lock, flags); m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); m += pll_info->m_offset; @@ -259,12 +256,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw) struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; - unsigned long flags; u32 ctl; - spin_lock_irqsave(&cgu->lock, flags); ctl = readl(cgu->base + pll_info->reg); - spin_unlock_irqrestore(&cgu->lock, flags); return !!(ctl & BIT(pll_info->enable_bit)); } @@ -562,16 +556,12 @@ static int ingenic_clk_is_enabled(struct clk_hw *hw) struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); struct ingenic_cgu *cgu = ingenic_clk->cgu; const struct ingenic_cgu_clk_info *clk_info; - unsigned long flags; int enabled = 1; clk_info = &cgu->clock_info[ingenic_clk->idx]; - if (clk_info->type & CGU_CLK_GATE) { - spin_lock_irqsave(&cgu->lock, flags); + if (clk_info->type & CGU_CLK_GATE) enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); - spin_unlock_irqrestore(&cgu->lock, flags); - } return enabled; }