From patchwork Thu May 28 15:27:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 199831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6009FC433E1 for ; Thu, 28 May 2020 15:29:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 42D3A208E4 for ; Thu, 28 May 2020 15:29:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=flygoat.com header.i=@flygoat.com header.b="mn9kjRnf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404438AbgE1P3K (ORCPT ); Thu, 28 May 2020 11:29:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404434AbgE1P3I (ORCPT ); Thu, 28 May 2020 11:29:08 -0400 Received: from vultr.net.flygoat.com (vultr.net.flygoat.com [IPv6:2001:19f0:6001:3633:5400:2ff:fe8c:553]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7562BC08C5C6; Thu, 28 May 2020 08:29:08 -0700 (PDT) Received: from localhost.localdomain (unknown [IPv6:2001:da8:20f:4430:250:56ff:fe9a:7470]) by vultr.net.flygoat.com (Postfix) with ESMTPSA id 67D9A20F12; Thu, 28 May 2020 15:29:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=vultr; t=1590679748; bh=LejHwNodx3fB5Z1MeLQOLJbRfsFmSQx2wh+M5DswtoA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mn9kjRnfol0AZFx++gXZ7/2uZZDkLmsWj9YmVwW7zlmJoFGj0/SpV1Kbhaf/+7QTq RxNEyAcvaQ2imXfqTG7mBJALKLpgG8rx5NrY4wS9VsYNFziLkOYt08FTwPz5pohXNL IpXa1SWKl8/tr3KN5nhBP79U5REpl2QI/pE4BRwSr3H7iXzS13/Hx1RgU2ZLi+OZED FUu08tJ+N/g4nawqIqL4gS9MABD/fEFfvcmkzMGi72a6RURg109FQw0om+2V+u2eB9 StyU3CKQrMIq0r6YkgsWx6VyjdWj2EzJtRlwLFidB+6s+ZQUDZFEFe6oKy/8IMUJXR X1JUotaZlsPvQ== From: Jiaxun Yang To: maz@kernel.org Cc: Jiaxun Yang , Rob Herring , Thomas Gleixner , Jason Cooper , Rob Herring , Huacai Chen , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v5 6/6] dt-bindings: interrupt-controller: Add Loongson PCH MSI Date: Thu, 28 May 2020 23:27:54 +0800 Message-Id: <20200528152757.1028711-7-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200528152757.1028711-1-jiaxun.yang@flygoat.com> References: <20200528152757.1028711-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for Loongson PCH MSI controller. Signed-off-by: Jiaxun Yang Reviewed-by: Rob Herring --- v5: Add range check for msi-base-vec & msi-num-vecs --- .../loongson,pch-msi.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml new file mode 100644 index 000000000000..1a5ebbdd219a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson PCH MSI Controller + +maintainers: + - Jiaxun Yang + +description: + This interrupt controller is found in the Loongson LS7A family of PCH for + transforming interrupts from PCIe MSI into HyperTransport vectorized + interrupts. + +properties: + compatible: + const: loongson,pch-msi-1.0 + + reg: + maxItems: 1 + + loongson,msi-base-vec: + description: + u32 value of the base of parent HyperTransport vector allocated + to PCH MSI. + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 255 + + loongson,msi-num-vecs: + description: + u32 value of the number of parent HyperTransport vectors allocated + to PCH MSI. + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 1 + maximum: 256 + + msi-controller: true + +required: + - compatible + - reg + - msi-controller + - loongson,msi-base-vec + - loongson,msi-num-vecs + +examples: + - | + #include + msi: msi-controller@2ff00000 { + compatible = "loongson,pch-msi-1.0"; + reg = <0x2ff00000 0x4>; + msi-controller; + loongson,msi-base-vec = <64>; + loongson,msi-num-vecs = <64>; + interrupt-parent = <&htvec>; + }; +...