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[83.6.167.130]) by smtp.googlemail.com with ESMTPSA id b81sm8922326wmc.5.2020.05.31.10.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 May 2020 10:28:11 -0700 (PDT) From: Konrad Dybcio Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/14] arm64: dts: Add a proper CPU map for MSM8992 Date: Sun, 31 May 2020 19:27:51 +0200 Message-Id: <20200531172804.256335-2-konradybcio@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200531172804.256335-1-konradybcio@gmail.com> References: <20200531172804.256335-1-konradybcio@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds cpu nodes for all 6 cores present on this SoC and the cpu-map. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 68 +++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 2021795c99ad..900c9445e0ba 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -20,11 +20,34 @@ / { cpus { #address-cells = <2>; #size-cells = <0>; + cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; }; }; @@ -33,11 +56,56 @@ CPU0: cpu@0 { compatible = "arm,cortex-a53"; reg = <0x0 0x0>; next-level-cache = <&L2_0>; + enable-method = "psci"; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; }; }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + next-level-cache = <&L2_1>; + enable-method = "psci"; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + next-level-cache = <&L2_1>; + enable-method = "psci"; + }; }; timer {