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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id m4sm8851731wro.18.2020.09.10.03.17.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 03:17:54 -0700 (PDT) From: Srinivas Kandagatla To: broonie@kernel.org Cc: lgirdwood@gmail.com, robh+dt@kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 6/8] ASoC: q6dsp: q6afe: update q6afe_set_param to support global clocks Date: Thu, 10 Sep 2020 11:17:30 +0100 Message-Id: <20200910101732.23484-7-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200910101732.23484-1-srinivas.kandagatla@linaro.org> References: <20200910101732.23484-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Previously there was no case where we need to set clock or send commands that are not associated with q6afe ports, now we have cases like clock voting and clock consumers like codecs that needed these clocks. update q6afe_set_param() to support such cases, including token passing. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/qdsp6/q6afe.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) -- 2.21.0 diff --git a/sound/soc/qcom/qdsp6/q6afe.c b/sound/soc/qcom/qdsp6/q6afe.c index 51c94dd9998d..9ed5537ee58e 100644 --- a/sound/soc/qcom/qdsp6/q6afe.c +++ b/sound/soc/qcom/qdsp6/q6afe.c @@ -967,14 +967,13 @@ static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt, return ret; } -static int q6afe_port_set_param(struct q6afe_port *port, void *data, - int param_id, int module_id, int psize) +static int q6afe_set_param(struct q6afe *afe, struct q6afe_port *port, + void *data, int param_id, int module_id, int psize, + int token) { struct afe_svc_cmd_set_param *param; struct afe_port_param_data_v2 *pdata; - struct q6afe *afe = port->afe; struct apr_pkt *pkt; - u16 port_id = port->id; int ret, pkt_size; void *p, *pl; @@ -995,7 +994,7 @@ static int q6afe_port_set_param(struct q6afe_port *port, void *data, pkt->hdr.pkt_size = pkt_size; pkt->hdr.src_port = 0; pkt->hdr.dest_port = 0; - pkt->hdr.token = port->token; + pkt->hdr.token = token; pkt->hdr.opcode = AFE_SVC_CMD_SET_PARAM; param->payload_size = sizeof(*pdata) + psize; @@ -1008,13 +1007,19 @@ static int q6afe_port_set_param(struct q6afe_port *port, void *data, ret = afe_apr_send_pkt(afe, pkt, port, AFE_SVC_CMD_SET_PARAM); if (ret) - dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", - port_id, ret); + dev_err(afe->dev, "AFE set params failed %d\n", ret); kfree(pkt); return ret; } +static int q6afe_port_set_param(struct q6afe_port *port, void *data, + int param_id, int module_id, int psize) +{ + return q6afe_set_param(port->afe, port, data, param_id, module_id, + psize, port->token); +} + static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data, int param_id, int module_id, int psize) { @@ -1064,7 +1069,7 @@ static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data, return ret; } -static int q6afe_set_lpass_clock(struct q6afe_port *port, +static int q6afe_port_set_lpass_clock(struct q6afe_port *port, struct afe_clk_cfg *cfg) { return q6afe_port_set_param_v2(port, cfg, @@ -1111,7 +1116,7 @@ int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, ccfg.clk_src = clk_src; ccfg.clk_root = clk_root; ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK1_VALID; - ret = q6afe_set_lpass_clock(port, &ccfg); + ret = q6afe_port_set_lpass_clock(port, &ccfg); break; case LPAIF_OSR_CLK: @@ -1120,7 +1125,7 @@ int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, ccfg.clk_src = clk_src; ccfg.clk_root = clk_root; ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID; - ret = q6afe_set_lpass_clock(port, &ccfg); + ret = q6afe_port_set_lpass_clock(port, &ccfg); break; case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR: case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1: