From patchwork Sat Oct 10 09:57:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 317596 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp3114702ilm; Sat, 10 Oct 2020 05:24:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzQvXvLLqC9VFkGbl95WtFbIPtWoguq0EE7R57qLEWBAHR7rZ41wwAHIBnbfe5i/Sv6njZM X-Received: by 2002:a05:6402:890:: with SMTP id e16mr4198344edy.272.1602332657885; Sat, 10 Oct 2020 05:24:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602332657; cv=none; d=google.com; s=arc-20160816; b=NAQ0L4FxSPNfkpDqPmpTAtVp6TgIwU1XN0/8B6l7hjzh8uvnYpIfhsKeyCIFdaEHtR cRnzHHdBumOaoO8om7TYY65D2aSQ2jdM00wW4v/ylYIuJlYXrNZOz74aaJ/BuRnbEdz/ 4nrd/fEu73PDXKa6gw+nPfJDVR4Y+mDO/2BybxCb7RDuX5JG9L7gCMixp+Co0UCuSt/3 g4us7SwZBqwjnZ/PYlVYCkCTX+DqU57aBMYkfDdwMLhTgpzJTY/7W4sdHspcbOFiMm99 ZwB/pV+aorX4ZoC+9VhwvL6xGMrwe2QrJCMqXz1pFuePUhmwZ7vfCC3n5VacatrQLenL RCLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=kL4onZ79jRTGY1zSp3AoIXTyK/wHoyJXcM88vYmzjTA=; b=LUdfWQwGjlUA+qh3uZXT8dX1HHz97YW4r3X7ZARWzebvZi775Ad/EERlcca+3tFZSZ wKdfar1nRquk3t+MIN0WX/QSW7lnmKaeoe4oHhxMJrD7moWgMVUPSgODUk+FLk1Mljt4 gNYQDnV+VCIOLFY6ek4fITpwfUvagJ5ogjY3OYSmcrTPptRAoTGTNsJbwoSV0Knz6UjY m7YqulslKTk+FF5Ar3YKvWgtey1TLYk5h9JIX1PJ6xEMPFmxukNwENnpgv+9DNx7dFEL 4gNXcW3eNYxRR90uTUWbhhHRkS5CwX5tg1+I92sxH3l6eHhHv3E1n4JzIAtFU9kdUBlg YzaQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e13si8434666edu.27.2020.10.10.05.24.17; Sat, 10 Oct 2020 05:24:17 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730074AbgJJMWo (ORCPT + 6 others); Sat, 10 Oct 2020 08:22:44 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:15258 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726923AbgJJKQM (ORCPT ); Sat, 10 Oct 2020 06:16:12 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id A0795FA2F258C4B7956E; Sat, 10 Oct 2020 17:57:46 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Sat, 10 Oct 2020 17:57:39 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 10/10] dt-bindings: arm: hisilicon: add missing properties into cpuctrl.yaml Date: Sat, 10 Oct 2020 17:57:09 +0800 Message-ID: <20201010095709.1340-11-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201010095709.1340-1-thunder.leizhen@huawei.com> References: <20201010095709.1340-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add properties: #address-cells, #size-cells and ranges. Due to the Hisilicon CPU controller node may contains child nodes, change the value of "additionalProperties" from "false" to "type: object". The corresponding examples are also added. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/controller/cpuctrl.yaml | 27 +++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) -- 1.8.3 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml index f6a314db3a59416..528dad4cde3cd19 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml @@ -21,9 +21,34 @@ properties: reg: maxItems: 1 + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + required: - compatible - reg -additionalProperties: false +additionalProperties: + type: object + +examples: + - | + cpuctrl@a22000 { + compatible = "hisilicon,cpuctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00a22000 0x2000>; + ranges = <0 0x00a22000 0x2000>; + + clock: clock@0 { + compatible = "hisilicon,hix5hd2-clock"; + reg = <0 0x2000>; + #clock-cells = <1>; + }; + }; ...