From patchwork Mon Oct 12 13:17:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 317633 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp4616848ilm; Mon, 12 Oct 2020 06:20:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzIJo11rhHNiiMqTBCtL2LAj/SVPW4aZ+Xs3UOBa2RCNZFqkIqabhBEOhz6rPRAyrZM4nDV X-Received: by 2002:aa7:dc18:: with SMTP id b24mr14403519edu.285.1602508806002; Mon, 12 Oct 2020 06:20:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602508805; cv=none; d=google.com; s=arc-20160816; b=vo2qMzMiawvDbw4lUeyBxGLD4QV9Rz1DQXSg1RkPX8VOCemya2/B1S7N5c4cKCnTMk 8+0T1WcvBnCzujerI6v5brLFHdDay/0r5OaxOQnA7684nEzXUEQygkKllMjCZ6N+GB8E kSJxqaDrdNKk7u5SXUPYqI2y7Q8VO40ecSvl+DQTgdZQcxU7P1hNBXp7IbcC/w7AhBwp O2h/5Ywa2myM9MeJvT6pQ5Oqohca82PIyfrmg0JXrysbgXd7lcBac4N2kmRSnVq5Q0jt 1xUNJuCbn2UMjbvNIyZWUbOyoojN02BYPv4fb7lasV9ySvwyzFxngDO21fV9jB1hMmpN PKSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=nPnPeqJfUPpUWYnp+1SgNMTLWJo/0M4HlOmNwYKWAm4=; b=09+dyhHqP6UITsP422ZKllKAhOu8Jii7fIMh4L/DC41cCNUbowT+kputR033L82FbI eJuZ90/Dc7SW05GpM8db40tIw7Z5uYxEzDKDPrgBi2BZf16mrhLJqWRajFzYJsRKSUQz 6dcxeTePqNNKRORicWclaGQlyG9p217bnHx5H4TivP3gMyXZ9ZpMnXslqjbmcEwxAUpt NUiYCwDHuihzBMCO8HEz2R1BNi9naHjTy6BpE0VBnr7aVsU1C1MOZ+KIyZiFbGyYngeg 0X6kvgebEzp9i8eE9ieNB9hSop8nqt7/OD9zoXCanq/wPsVCdnfLf30s7TPXUCmBgxt7 39kw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dp1si12424524ejc.606.2020.10.12.06.20.05; Mon, 12 Oct 2020 06:20:05 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388389AbgJLNTt (ORCPT + 6 others); Mon, 12 Oct 2020 09:19:49 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:15279 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388892AbgJLNTh (ORCPT ); Mon, 12 Oct 2020 09:19:37 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C9C39797ABAAB2713AE6; Mon, 12 Oct 2020 21:19:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.134) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Mon, 12 Oct 2020 21:19:29 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH 11/11] arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml Date: Mon, 12 Oct 2020 21:17:39 +0800 Message-ID: <20201012131739.1655-12-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20201012131739.1655-1-thunder.leizhen@huawei.com> References: <20201012131739.1655-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.134] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The snps,dw-apb-uart binding need to specify two clocks: "baudclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 1.8.3 diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 26caf09e9511b3c..c073d6d8b55c0b4 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -300,8 +300,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk200mhz>, <&refclk200mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -311,8 +311,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x0 0x80310000 0x0 0x10000>; interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk200mhz>, <&refclk200mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled";