diff mbox series

[v4,02/11] arm64: dts: ls1043a: add DT node for external interrupt lines

Message ID 20201130101515.27431-2-biwen.li@oss.nxp.com
State Superseded
Headers show
Series [v4,01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external interrupt | expand

Commit Message

Biwen Li (OSS) Nov. 30, 2020, 10:15 a.m. UTC 
From: Biwen Li <biwen.li@nxp.com>

Add device-tree node for external interrupt lines IRQ0-IRQ11.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
Change in v4:
	- remove copyright to fix corrupt

Change in v3:
	- none

Change in v2:
	- none

 .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

Comments

Shawn Guo Jan. 5, 2021, 1:45 a.m. UTC | #1 
On Mon, Nov 30, 2020 at 06:15:06PM +0800, Biwen Li wrote:
> From: Biwen Li <biwen.li@nxp.com>

> 

> Add device-tree node for external interrupt lines IRQ0-IRQ11.

> 

> Signed-off-by: Biwen Li <biwen.li@nxp.com>


Applied 2 ~ 10, thanks.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 0464b8aa4bc4..573e6659cff8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -311,6 +311,31 @@ 
 			compatible = "fsl,ls1043a-scfg", "syscon";
 			reg = <0x0 0x1570000 0x0 0x10000>;
 			big-endian;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0x1570000 0x10000>;
+
+			extirq: interrupt-controller@1ac {
+				compatible = "fsl,ls1043a-extirq";
+				#interrupt-cells = <2>;
+				#address-cells = <0>;
+				interrupt-controller;
+				reg = <0x1ac 4>;
+				interrupt-map =
+					<0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					<1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+					<2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					<3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					<4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+					<5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+					<6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+					<8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+					<10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					<11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-map-mask = <0xffffffff 0x0>;
+			};
 		};
 
 		crypto: crypto@1700000 {