From patchwork Fri Dec 4 05:43:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 337723 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp897229ilb; Thu, 3 Dec 2020 21:46:19 -0800 (PST) X-Google-Smtp-Source: ABdhPJypKUM4jmtBOYS6QOiLTC81PVkgoAd1ylAzS9GHeBRzR3xkevZYwFeiMjX+TVFvq+1Orf9v X-Received: by 2002:a17:906:22c7:: with SMTP id q7mr5615318eja.486.1607060779076; Thu, 03 Dec 2020 21:46:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607060779; cv=none; d=google.com; s=arc-20160816; b=sm3KnLCmFiAf0tyFCNxC6gos0FZj0jGABYlLQCuShIJwDa6tR5YlX2F1f8F8b0h0ze RQb3aBs5svstyNbXx5GOfrXjFDIuJsKYAoxLH8VJcF+T58G+BEP0Jr0rYsTbEbpki2TV UzWBXEH2naO7DcuT0pQFu7IEylSUXQFmgRngEO65FuwxGyw9TFpYZBkjiZw1UFzSXAoe tVwpgn3IvpfZxVCJkPGbCV96Hu5TF436nRIrvq+pQoO5qd8CsnWeaKUNAS4lVBBkh2hX A9mGnx0g56J7McU4VzCqXarpTybqXLE85BMsijzim29YTI6wzsG4eAj+HpJXyhz/pqIA He9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=t4xGa2Pnc9z/hfTgVv9bsqX6Gv/zhfLGEpkB0DIHVbI=; b=I3sUF3dvLivEf1G4ZlProwE/htDX5hV89WSO1EV0LTXlT598CCvwKvpxETQnvTOyvE 0dVtM1vMWMyK9l3ushS3SR/S1kECO8vGQSrGhqXx3w9kRc/N8t7vksk/aDW6fWG3FS+f C4A3UILaInqHO2hVl1pyLhWzIHlL1UCvW0QyHq8jtob1OzWz/FEGq6M5aKN0tzt0MKLT chYvNDlAun4H88F+FREl/fUIWvH6Yyw0kv4hCCGVYVyW925DLn7NY9A3yEAM/v5iRDlH XMlMUarNIX27F+qkrsjGaHGMFFWYdDpFC8F5KQxw4JtXSlceGKBD4N0dPHwrLqiiGazZ iP2g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id aq15si733626ejc.523.2020.12.03.21.46.18; Thu, 03 Dec 2020 21:46:19 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727963AbgLDFos (ORCPT + 6 others); Fri, 4 Dec 2020 00:44:48 -0500 Received: from mail.kernel.org ([198.145.29.99]:50238 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727892AbgLDFos (ORCPT ); Fri, 4 Dec 2020 00:44:48 -0500 From: Vinod Koul Authentication-Results: mail.kernel.org; dkim=permerror (bad message/signature format) To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Andy Gross , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] arm64: dts: qcom: Add basic devicetree support for SM8350 SoC Date: Fri, 4 Dec 2020 11:13:46 +0530 Message-Id: <20201204054347.2877857-4-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201204054347.2877857-1-vkoul@kernel.org> References: <20201204054347.2877857-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add basic devicetree support for Qualcomm Technologies, Inc SM8350 SoC. This adds gcc, pinctrl, reserved memory, uart, cpu nodes for this SoC. Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 496 +++++++++++++++++++++++++++ 1 file changed, 496 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8350.dtsi -- 2.26.2 diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi new file mode 100644 index 000000000000..9e4bb29abe62 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Linaro Limaited + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo485"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: memory@80860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + + reserved_xbl_uefi_log: memory@80880000 { + reg = <0x0 0x80880000 0x0 0x14000>; + no-map; + }; + + smem_mem: memory@80900000 { + reg = <0x0 0x80900000 0x0 0x200000>; + no-map; + }; + + cpucp_fw_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap: memory@80c00000 { + reg = <0x0 0x80c00000 0x0 0x4600000>; + no-map; + }; + + pil_camera_mem: mmeory@85200000 { + reg = <0x0 0x85200000 0x0 0x500000>; + no-map; + }; + + pil_video_mem: memory@85700000 { + reg = <0x0 0x85700000 0x0 0x500000>; + no-map; + }; + + pil_cvp_mem: memory@85c00000 { + reg = <0x0 0x85c00000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: memory@86100000 { + reg = <0x0 0x86100000 0x0 0x2100000>; + no-map; + }; + + pil_slpi_mem: memory@88200000 { + reg = <0x0 0x88200000 0x0 0x1500000>; + no-map; + }; + + pil_cdsp_mem: memory@89700000 { + reg = <0x0 0x89700000 0x0 0x1e00000>; + no-map; + }; + + pil_ipa_fw_mem: memory@8b500000 { + reg = <0x0 0x8b500000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@8b510000 { + reg = <0x0 0x8b510000 0x0 0xa000>; + no-map; + }; + + pil_gpu_mem: memory@8b51a000 { + reg = <0x0 0x8b51a000 0x0 0x2000>; + no-map; + }; + + pil_spss_mem: memory@8b600000 { + reg = <0x0 0x8b600000 0x0 0x100000>; + no-map; + }; + + pil_modem_mem: memory@8b800000 { + reg = <0x0 0x8b800000 0x0 0x10000000>; + no-map; + }; + + hyp_reserved_mem: memory@d0000000 { + reg = <0x0 0xd0000000 0x0 0x800000>; + no-map; + }; + + pil_trustedvm_mem: memory@d0800000 { + reg = <0x0 0xd0800000 0x0 0x76f7000>; + no-map; + }; + + qrtr_shbuf: memory@d7ef7000 { + reg = <0x0 0xd7ef7000 0x0 0x9000>; + no-map; + }; + + chan0_shbuf: memory@d7f00000 { + reg = <0x0 0xd7f00000 0x0 0x80000>; + no-map; + }; + + chan1_shbuf: memory@d7f80000 { + reg = <0x0 0xd7f80000 0x0 0x80000>; + no-map; + }; + + removed_mem: memory@d8800000 { + reg = <0x0 0xd8800000 0x0 0x6800000>; + no-map; + }; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sm8350"; + reg = <0x0 0x00100000 0x0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + }; + + ipcc: mailbox@408000 { + compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + qupv3_id_1: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart2: serial@98c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x0098c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart3_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8350-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, + <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, + <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, + <156 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + aoss_qmp: qmp@c300000 { + compatible = "qcom,sm8350-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sm8350-pinctrl"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 203>; + + qup_uart3_default: qup-uart3-default { + mux { + pins = "gpio18", "gpio19"; + function = "qup3"; + }; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + timer@17c20000 { + #address-cells = <2>; + #size-cells = <2>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0 0x17c21000 0x0 0x1000>, + <0x0 0x17c22000 0x0 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x0 0x17c23000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x0 0x17c25000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x0 0x17c27000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x0 0x17c29000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x0 0x17c2b000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x0 0x17c2d000 0x0 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + + rpmhcc: clock-controller { + compatible = "qcom,sm8350-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +};