From patchwork Tue Dec 22 07:05:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 346617 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5095946jai; Mon, 21 Dec 2020 23:08:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJyUd0ZBaGfN7tNBZkD+FUIInf3jn4CBfX+GJcF0za65R3yxAxcc/hJexjIF2RkpOaGnlH1P X-Received: by 2002:a17:906:a008:: with SMTP id p8mr5680772ejy.117.1608620887428; Mon, 21 Dec 2020 23:08:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1608620887; cv=none; d=google.com; s=arc-20160816; b=AcaM7tBXzcC0qOCx2S7cdOCTcQzEvY1PL3ONqoogFpsWTD7AfpqeGaApegxahB/2LS JDlzoJffsqzsOgTKKpnTIwqT06AcqBPj+0gnVnAi654hqZL4mXF3R/Xu8STPjplREMzo 6Kg/4jckUdx/rxy19wPnewcUW7IRDfwn5zPENgV+/RsNg+jzk+a7onvmabjvwWII8diZ 2vol+pCN4UjmBK6qTe2Blg7pDbgcyqTIZkjDCKdubpAierJPuwAqVss8UPWTGKt5MZvZ Lntu/Eoybk6e6K3/3HeBhUG9NU0GAGPChVVZrreAYT4skT/NoVejE5HlktTY4UlFh1FT A1tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=14cbnSxHB44iZkpTWbvcT9c4bCPw1pt8QKkVr6DRwOw=; b=YD/uhEnrfs9cbMPyDKDLDbNOng/LiNV2pOiEXw3G60AzD8BeNTzyPpfBq5DvYt5XeD RTgRanwNwj/tC/59h7hWQOCZVNnZpcg7ZGCyZfdBLlGuDTMcKdOSKbln1RZ2xAR8f+R/ 28gR5q5r8tYz9WkBXqLQHUgOdD8wpq8sdM/N/uz5nsClciKgydy+CZRuikXzc4PC9qBQ ceTv3iLQG5UcWow/x0p7lzy6mJCM3MbE2cnNtC6cf+Dc/QC04SPESRfIbZH9eq601QbL hIS++pGBfQ+5ULnJQovTs3X3yASafme0WjK2XAj6bfw7aV6abmXVMLHuweUfXa3GKSSI N0Pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vR+rr+Zo; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h4si1408831edf.490.2020.12.21.23.08.07; Mon, 21 Dec 2020 23:08:07 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vR+rr+Zo; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726427AbgLVHHS (ORCPT + 7 others); Tue, 22 Dec 2020 02:07:18 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:54106 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725885AbgLVHHR (ORCPT ); Tue, 22 Dec 2020 02:07:17 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BM76Dei064338; Tue, 22 Dec 2020 01:06:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608620773; bh=14cbnSxHB44iZkpTWbvcT9c4bCPw1pt8QKkVr6DRwOw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vR+rr+Zo9MLESkQRQA67Sk6S3ilWJuNq0VwR9tEt+70u0mwTWOwOLTcCUQDiXTWlH tIOXclliAv+AzLDJV5I7y6af6pkTkKY5aV1kyHfS2T+S4zlHtbwdffHVIpweF6lvrT g4/uw9mIJP3y4ADuhYUvIwCzHF2m3SaHxr1BI8oE= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BM76DvR109324 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Dec 2020 01:06:13 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 22 Dec 2020 01:06:12 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 22 Dec 2020 01:06:12 -0600 Received: from a0393678-ssd.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BM75N7M050344; Tue, 22 Dec 2020 01:06:09 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Swapnil Jakhade , , , CC: Nishanth Menon , Philipp Zabel Subject: [PATCH v2 13/14] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES Date: Tue, 22 Dec 2020 12:35:19 +0530 Message-ID: <20201222070520.28132-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201222070520.28132-1-kishon@ti.com> References: <20201222070520.28132-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use external clock for all the SERDES used by PCIe controller. This will make the same clock used by the local SERDES as well as the clock provided to the PCIe connector. Signed-off-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j721e-common-proc-board.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 86f7ab511ee8..788126daf91c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -639,6 +639,51 @@ clock-frequency = <100000000>; }; +&wiz0_pll1_refclk { + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz0_refclk_dig { + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes0_pll_cmnlc { + assigned-clocks = <&serdes0_pll_cmnlc>; + assigned-clock-parents = <&serdes0_refrcv1>; +}; + +&wiz1_pll1_refclk { + assigned-clocks = <&wiz1_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz1_refclk_dig { + assigned-clocks = <&wiz1_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes1_pll_cmnlc { + assigned-clocks = <&serdes1_pll_cmnlc>; + assigned-clock-parents = <&serdes1_refrcv1>; +}; + +&wiz2_pll1_refclk { + assigned-clocks = <&wiz2_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz2_refclk_dig { + assigned-clocks = <&wiz2_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes2_pll_cmnlc { + assigned-clocks = <&serdes2_pll_cmnlc>; + assigned-clock-parents = <&serdes2_refrcv1>; +}; + &serdes0 { serdes0_pcie_link: link@0 { reg = <0>;