[v2,01/14] phy: cadence: Sierra: Fix PHY power_on sequence

Message ID	20201222070520.28132-2-kishon@ti.com
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; From: Kishon Vijay Abraham I <kishon@ti.com> To: Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>, Swapnil Jakhade <sjakhade@cadence.com>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> CC: Nishanth Menon <nm@ti.com>, Philipp Zabel <p.zabel@pengutronix.de>, <stable@vger.kernel.org> Subject: [PATCH v2 01/14] phy: cadence: Sierra: Fix PHY power_on sequence Date: Tue, 22 Dec 2020 12:35:07 +0530 Message-ID: <20201222070520.28132-2-kishon@ti.com> In-Reply-To: <20201222070520.28132-1-kishon@ti.com> References: <20201222070520.28132-1-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk
Series	PHY: Add support in Sierra to use external clock \| expand [v2,00/14] PHY: Add support in Sierra to use external clock [v2,01/14] phy: cadence: Sierra: Fix PHY power_on sequence [v2,02/14] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() [v2,03/14] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES [v2,04/14] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode [v2,05/14] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes [v2,06/14] phy: cadence: cadence-sierra: Move all clk_get_() to a separate function [v2,07/14] phy: cadence: cadence-sierra: Move all reset_control_get() to a separate function [v2,08/14] phy: cadence: cadence-sierra: Explicitly request exclusive reset control [v2,09/14] phy: cadence: sierra: Model reference receiver as clocks (gate clocks) [v2,10/14] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks [v2,11/14] arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES [v2,12/14] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES [v2,13/14] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES [v2,14/14] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy"

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20201222070520.28132-2-kishon@ti.com

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Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org
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	client-ip=23.128.96.18; 
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>,
	Rob Herring <robh+dt@kernel.org>, Swapnil Jakhade <sjakhade@cadence.com>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
CC: Nishanth Menon <nm@ti.com>, Philipp Zabel <p.zabel@pengutronix.de>,
	<stable@vger.kernel.org>
Subject: [PATCH v2 01/14] phy: cadence: Sierra: Fix PHY power_on sequence
Date: Tue, 22 Dec 2020 12:35:07 +0530
Message-ID: <20201222070520.28132-2-kishon@ti.com>
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References: <20201222070520.28132-1-kishon@ti.com>
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Series

PHY: Add support in Sierra to use external clock | expand

Commit Message

Kishon Vijay Abraham I Dec. 22, 2020, 7:05 a.m. UTC

Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.

Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

Cc: <stable@vger.kernel.org> # v5.4+
---
 drivers/phy/cadence/phy-cadence-sierra.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

-- 
2.17.1

diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 26a0badabe38..19f32ae877b9 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -319,6 +319,12 @@  static int cdns_sierra_phy_on(struct phy *gphy)
 	u32 val;
 	int ret;
 
+	ret = reset_control_deassert(sp->phy_rst);
+	if (ret) {
+		dev_err(dev, "Failed to take the PHY out of reset\n");
+		return ret;
+	}
+
 	/* Take the PHY lane group out of reset */
 	ret = reset_control_deassert(ins->lnk_rst);
 	if (ret) {
@@ -616,7 +622,6 @@  static int cdns_sierra_phy_probe(struct platform_device *pdev)
 
 	pm_runtime_enable(dev);
 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-	reset_control_deassert(sp->phy_rst);
 	return PTR_ERR_OR_ZERO(phy_provider);
 
 put_child:

[v2,01/14] phy: cadence: Sierra: Fix PHY power_on sequence

Commit Message

Patch