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[23.128.96.18]) by mx.google.com with ESMTP id t20si33458073edw.31.2021.01.05.07.16.45; Tue, 05 Jan 2021 07:16:45 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rBfQDRX0; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726098AbhAEPQV (ORCPT + 6 others); Tue, 5 Jan 2021 10:16:21 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:40064 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725868AbhAEPQR (ORCPT ); Tue, 5 Jan 2021 10:16:17 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 105FEcCH012839; Tue, 5 Jan 2021 09:14:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1609859678; bh=bcKpGUBe0fOJfXDJUBX9rPDmhCuFi5ZCwNpQdzadubE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rBfQDRX0DQ6wdijIOkQWDleNg9VO27UwJbfde0J46a59+V/Lt2bG+iNWr65YfvNzB yPGhI4iMvjvGh/vD8K6rZ0klheyW9NFMmEHbgsxynI2M6aWZcxX04BjfMtQA8dd78t ts8QH/gEc3V92LAzi/mxITfwTzunKH7KutigSVTU= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 105FEcNV036071 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 5 Jan 2021 09:14:38 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 5 Jan 2021 09:14:37 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 5 Jan 2021 09:14:37 -0600 Received: from a0393678-ssd.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 105FEPOF005961; Tue, 5 Jan 2021 09:14:35 -0600 From: Kishon Vijay Abraham I To: Nishanth Menon , Rob Herring , Kishon Vijay Abraham I CC: , , Subject: [PATCH v4 3/6] arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node Date: Tue, 5 Jan 2021 20:44:18 +0530 Message-ID: <20210105151421.23237-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210105151421.23237-1-kishon@ti.com> References: <20210105151421.23237-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, CPSW (SGMII/QSGMII) and USB. Signed-off-by: Kishon Vijay Abraham I --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 63 +++++++++++++++++++++++ 1 file changed, 63 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index b0094212aa82..fbe4cd1e6e09 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -5,6 +5,13 @@ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ */ +/ { + serdes_refclk: serdes-refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -531,6 +538,62 @@ dma-coherent; }; + serdes_wiz0: wiz@5060000 { + compatible = "ti,j721e-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks = <&k3_clks 292 85>; + assigned-clock-parents = <&k3_clks 292 89>; + + wiz0_pll0_refclk: pll0-refclk { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_pll0_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll0_refclk>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_pll1_refclk: pll1-refclk { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_pll1_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_refclk_dig: refclk-dig { + clocks = <&k3_clks 292 85>, <&serdes_refclk>; + clock-output-names = "wiz0_refclk_dig"; + #clock-cells = <0>; + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&k3_clks 292 85>; + }; + + wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { + clocks = <&wiz0_refclk_dig>; + #clock-cells = <0>; + }; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&wiz0_pll0_refclk>; + clock-names = "refclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x4104000 0x00 0x100>;