diff mbox series

[v3,1/4] clk: axi-clkgen: replace ARCH dependencies with driver deps

Message ID 20210201151245.21845-2-alexandru.ardelean@analog.com
State New
Headers show
Series [v3,1/4] clk: axi-clkgen: replace ARCH dependencies with driver deps | expand

Commit Message

Alexandru Ardelean Feb. 1, 2021, 3:12 p.m. UTC
The intent is to be able to run this driver to access the IP core in setups
where FPGA board is also connected via a PCIe bus. In such cases the number
of combinations explodes, where the host system can be an x86 with Xilinx
Zynq/ZynqMP/Microblaze board connected via PCIe.
Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.

To accommodate for these cases, this change removes the limitation for this
driver to be compilable only on Zynq/Microblaze architectures.
And adds dependencies on the mechanisms required by the driver to work (OF
and HAS_IOMEM).

Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
 drivers/clk/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Michal Simek Feb. 1, 2021, 3:15 p.m. UTC | #1
On 2/1/21 4:12 PM, Alexandru Ardelean wrote:
> The intent is to be able to run this driver to access the IP core in setups
> where FPGA board is also connected via a PCIe bus. In such cases the number
> of combinations explodes, where the host system can be an x86 with Xilinx
> Zynq/ZynqMP/Microblaze board connected via PCIe.
> Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
> 
> To accommodate for these cases, this change removes the limitation for this
> driver to be compilable only on Zynq/Microblaze architectures.
> And adds dependencies on the mechanisms required by the driver to work (OF
> and HAS_IOMEM).
> 
> Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> ---
>  drivers/clk/Kconfig | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 85856cff506c..cee1d4e657bc 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -247,7 +247,8 @@ config CLK_TWL6040
>  
>  config COMMON_CLK_AXI_CLKGEN
>  	tristate "AXI clkgen driver"
> -	depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
> +	depends on HAS_IOMEM || COMPILE_TEST
> +	depends on OF
>  	help
>  	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
>  	  FPGAs. It is commonly used in Analog Devices' reference designs.
> 

Make sense.

Acked-by: Michal Simek <michal.simek@xilinx.com>

Thanks,
Michal
Moritz Fischer Feb. 2, 2021, 4:21 a.m. UTC | #2
On Mon, Feb 01, 2021 at 05:12:42PM +0200, Alexandru Ardelean wrote:
> The intent is to be able to run this driver to access the IP core in setups

> where FPGA board is also connected via a PCIe bus. In such cases the number

> of combinations explodes, where the host system can be an x86 with Xilinx

> Zynq/ZynqMP/Microblaze board connected via PCIe.

> Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.

> 

> To accommodate for these cases, this change removes the limitation for this

> driver to be compilable only on Zynq/Microblaze architectures.

> And adds dependencies on the mechanisms required by the driver to work (OF

> and HAS_IOMEM).

> 

> Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>

> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>

Reviewed-by: Moritz Fischer <mdf@kernel.org>

> ---

>  drivers/clk/Kconfig | 3 ++-

>  1 file changed, 2 insertions(+), 1 deletion(-)

> 

> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig

> index 85856cff506c..cee1d4e657bc 100644

> --- a/drivers/clk/Kconfig

> +++ b/drivers/clk/Kconfig

> @@ -247,7 +247,8 @@ config CLK_TWL6040

>  

>  config COMMON_CLK_AXI_CLKGEN

>  	tristate "AXI clkgen driver"

> -	depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST

> +	depends on HAS_IOMEM || COMPILE_TEST

> +	depends on OF

>  	help

>  	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx

>  	  FPGAs. It is commonly used in Analog Devices' reference designs.

> -- 

> 2.17.1

> 


Thanks,
Moritz
Stephen Boyd Feb. 9, 2021, 2:28 a.m. UTC | #3
Quoting Alexandru Ardelean (2021-02-01 07:12:42)
> The intent is to be able to run this driver to access the IP core in setups

> where FPGA board is also connected via a PCIe bus. In such cases the number

> of combinations explodes, where the host system can be an x86 with Xilinx

> Zynq/ZynqMP/Microblaze board connected via PCIe.

> Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.

> 

> To accommodate for these cases, this change removes the limitation for this

> driver to be compilable only on Zynq/Microblaze architectures.

> And adds dependencies on the mechanisms required by the driver to work (OF

> and HAS_IOMEM).

> 

> Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>

> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>

> ---


Applied to clk-next
diff mbox series

Patch

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 85856cff506c..cee1d4e657bc 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -247,7 +247,8 @@  config CLK_TWL6040
 
 config COMMON_CLK_AXI_CLKGEN
 	tristate "AXI clkgen driver"
-	depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
+	depends on HAS_IOMEM || COMPILE_TEST
+	depends on OF
 	help
 	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
 	  FPGAs. It is commonly used in Analog Devices' reference designs.