diff mbox series

[01/13] arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phy

Message ID 20210225141022.1.Iad06142ceb8426ce5492737bf3d9162ed0dd2b55@changeid
State New
Headers show
Series [01/13] arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phy | expand

Commit Message

Doug Anderson Feb. 25, 2021, 10:12 p.m. UTC
From: Stephen Boyd <swboyd@chromium.org>

Drop the old node and add the new one in its place.

Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
[dianders: Adjusted due to DP not itself not in upstream dts yet]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---

 arch/arm64/boot/dts/qcom/sc7180.dtsi | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

Comments

Dmitry Baryshkov March 14, 2021, 12:28 a.m. UTC | #1
On 26/02/2021 01:12, Douglas Anderson wrote:
> From: Stephen Boyd <swboyd@chromium.org>

> 

> Drop the old node and add the new one in its place.

> 

> Cc: Stephen Boyd <swboyd@chromium.org>

> Cc: Jeykumar Sankaran <jsanka@codeaurora.org>

> Cc: Chandan Uddaraju <chandanu@codeaurora.org>

> Cc: Vara Reddy <varar@codeaurora.org>

> Cc: Tanmay Shah <tanmay@codeaurora.org>

> Cc: Rob Clark <robdclark@chromium.org>

> Signed-off-by: Stephen Boyd <swboyd@chromium.org>

> [dianders: Adjusted due to DP not itself not in upstream dts yet]

> Signed-off-by: Douglas Anderson <dianders@chromium.org>

> ---

> 

>   arch/arm64/boot/dts/qcom/sc7180.dtsi | 23 ++++++++++++++++-------

>   1 file changed, 16 insertions(+), 7 deletions(-)

> 

> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi

> index 1ea3344ab62c..60248a6757d8 100644

> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi

> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi

> @@ -2770,12 +2770,11 @@ usb_1_hsphy: phy@88e3000 {

>   		};

>   

>   		usb_1_qmpphy: phy-wrapper@88e9000 {

> -			compatible = "qcom,sc7180-qmp-usb3-phy";

> +			compatible = "qcom,sc7180-qmp-usb3-dp-phy";

>   			reg = <0 0x088e9000 0 0x18c>,

> -			      <0 0x088e8000 0 0x38>;

> -			reg-names = "reg-base", "dp_com";

> +			      <0 0x088e8000 0 0x38>,


Technically this should be 0x3c. Offset 0x38 is USB3_DP_COM_REVISION_ID3 
(not used by the current driver though).

> +			      <0 0x088ea000 0 0x40>;


I think 0x40 is not enough here.
This is a serdes region and qmp_v3_dp_serdes_tbl contains registers 
0x148 and 0x154.

>   			status = "disabled";

> -			#clock-cells = <1>;

>   			#address-cells = <2>;

>   			#size-cells = <2>;

>   			ranges;

> @@ -2790,7 +2789,7 @@ usb_1_qmpphy: phy-wrapper@88e9000 {

>   				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;

>   			reset-names = "phy", "common";

>   

> -			usb_1_ssphy: phy@88e9200 {

> +			usb_1_ssphy: usb3-phy@88e9200 {

>   				reg = <0 0x088e9200 0 0x128>,

>   				      <0 0x088e9400 0 0x200>,

>   				      <0 0x088e9c00 0 0x218>,

> @@ -2803,6 +2802,16 @@ usb_1_ssphy: phy@88e9200 {

>   				clock-names = "pipe0";

>   				clock-output-names = "usb3_phy_pipe_clk_src";

>   			};

> +

> +			dp_phy: dp-phy@88ea200 {

> +				reg = <0 0x088ea200 0 0x200>,

> +				      <0 0x088ea400 0 0x200>,

> +				      <0 0x088eaa00 0 0x200>,

> +				      <0 0x088ea600 0 0x200>,

> +				      <0 0x088ea800 0 0x200>;

> +				#clock-cells = <1>;

> +				#phy-cells = <0>;

> +			};

>   		};

>   

>   		dc_noc: interconnect@9160000 {

> @@ -3166,8 +3175,8 @@ dispcc: clock-controller@af00000 {

>   				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,

>   				 <&dsi_phy 0>,

>   				 <&dsi_phy 1>,

> -				 <0>,

> -				 <0>;

> +				 <&dp_phy 0>,

> +				 <&dp_phy 1>;

>   			clock-names = "bi_tcxo",

>   				      "gcc_disp_gpll0_clk_src",

>   				      "dsi0_phy_pll_out_byteclk",

> 



-- 
With best wishes
Dmitry
Doug Anderson March 15, 2021, 5:40 p.m. UTC | #2
Hi,

On Sat, Mar 13, 2021 at 4:28 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>

> >               usb_1_qmpphy: phy-wrapper@88e9000 {

> > -                     compatible = "qcom,sc7180-qmp-usb3-phy";

> > +                     compatible = "qcom,sc7180-qmp-usb3-dp-phy";

> >                       reg = <0 0x088e9000 0 0x18c>,

> > -                           <0 0x088e8000 0 0x38>;

> > -                     reg-names = "reg-base", "dp_com";

> > +                           <0 0x088e8000 0 0x38>,

>

> Technically this should be 0x3c. Offset 0x38 is USB3_DP_COM_REVISION_ID3

> (not used by the current driver though).

>

> > +                           <0 0x088ea000 0 0x40>;

>

> I think 0x40 is not enough here.

> This is a serdes region and qmp_v3_dp_serdes_tbl contains registers

> 0x148 and 0x154.


OK!

https://lore.kernel.org/r/20210315103836.1.I9a97120319d43b42353aeac4d348624d60687df7@changeid

-Doug
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 1ea3344ab62c..60248a6757d8 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2770,12 +2770,11 @@  usb_1_hsphy: phy@88e3000 {
 		};
 
 		usb_1_qmpphy: phy-wrapper@88e9000 {
-			compatible = "qcom,sc7180-qmp-usb3-phy";
+			compatible = "qcom,sc7180-qmp-usb3-dp-phy";
 			reg = <0 0x088e9000 0 0x18c>,
-			      <0 0x088e8000 0 0x38>;
-			reg-names = "reg-base", "dp_com";
+			      <0 0x088e8000 0 0x38>,
+			      <0 0x088ea000 0 0x40>;
 			status = "disabled";
-			#clock-cells = <1>;
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
@@ -2790,7 +2789,7 @@  usb_1_qmpphy: phy-wrapper@88e9000 {
 				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
 			reset-names = "phy", "common";
 
-			usb_1_ssphy: phy@88e9200 {
+			usb_1_ssphy: usb3-phy@88e9200 {
 				reg = <0 0x088e9200 0 0x128>,
 				      <0 0x088e9400 0 0x200>,
 				      <0 0x088e9c00 0 0x218>,
@@ -2803,6 +2802,16 @@  usb_1_ssphy: phy@88e9200 {
 				clock-names = "pipe0";
 				clock-output-names = "usb3_phy_pipe_clk_src";
 			};
+
+			dp_phy: dp-phy@88ea200 {
+				reg = <0 0x088ea200 0 0x200>,
+				      <0 0x088ea400 0 0x200>,
+				      <0 0x088eaa00 0 0x200>,
+				      <0 0x088ea600 0 0x200>,
+				      <0 0x088ea800 0 0x200>;
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+			};
 		};
 
 		dc_noc: interconnect@9160000 {
@@ -3166,8 +3175,8 @@  dispcc: clock-controller@af00000 {
 				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
 				 <&dsi_phy 0>,
 				 <&dsi_phy 1>,
-				 <0>,
-				 <0>;
+				 <&dp_phy 0>,
+				 <&dp_phy 1>;
 			clock-names = "bi_tcxo",
 				      "gcc_disp_gpll0_clk_src",
 				      "dsi0_phy_pll_out_byteclk",