From patchwork Wed Mar 31 20:42:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 413004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78CE1C43462 for ; Wed, 31 Mar 2021 20:44:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2E9DD61077 for ; Wed, 31 Mar 2021 20:44:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236643AbhCaUnd (ORCPT ); Wed, 31 Mar 2021 16:43:33 -0400 Received: from st43p00im-zteg10073401.me.com ([17.58.63.181]:36922 "EHLO st43p00im-zteg10073401.me.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236663AbhCaUnV (ORCPT ); Wed, 31 Mar 2021 16:43:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1617223400; bh=Ge/uIA5hLdNP9ltZO4wkWhRW01e4mo9aC5X6GiyNNoM=; h=From:To:Subject:Date:Message-Id; b=A2MJjRYIsjeyQwa37OksOOVr3ar5NfnyVeavS1lylH3X/IiYbAEw8Hvob+lqCHzTL UD6K6JlYNelXYAE0l656lGv2z6k3csHwhSp1y4EfP5Ay5Jv+TEpj7c7l0QrdCnVek8 ga4JNbykSHi3j7zhAUSnuqcToXtm11eikhmNPx1C9q365dmFm6t5M5yTWA8DhEoz4T hEXemnDiKV2hwrwkPe5Nbs1C+Fp21WVUzvZXd3mXYCRD+H0TdLtNkBW9oHKbJFGzSQ bMMzLlFeO9GoCT3dRS4grqZE6CP+MAQTCGmh4ydc+wNSnK4LWHDmpWdxQ6RKh+tLrz Glulmty+ORPYw== Received: from localhost (101.220.150.77.rev.sfr.net [77.150.220.101]) by st43p00im-zteg10073401.me.com (Postfix) with ESMTPSA id F1AC85E03FF; Wed, 31 Mar 2021 20:43:19 +0000 (UTC) From: Alain Volmat To: Patrice Chotard , Rob Herring Cc: Arnd Bergmann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avolmat@me.com Subject: [PATCH v3 04/13] ARM: dts: sti: update clkgen-pll entries in stih407-clock Date: Wed, 31 Mar 2021 22:42:19 +0200 Message-Id: <20210331204228.26107-5-avolmat@me.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210331204228.26107-1-avolmat@me.com> References: <20210331204228.26107-1-avolmat@me.com> X-Proofpoint-Virus-Version: =?utf-8?q?vendor=3Dfsecure_engine=3D1=2E1=2E1?= =?utf-8?q?70-22c6f66c430a71ce266a39bfe25bc2903e8d5c8f=3A6=2E0=2E36?= =?utf-8?b?OSwxOC4wLjc2MSwxNy4wLjYwNy40NzUuMDAwMDAwMCBkZWZpbml0aW9u?= =?utf-8?q?s=3D2021-03-31=5F08=3A2021-03-31=5F02=2C2021-03-31=5F08?= =?utf-8?q?=2C2020-04-07=5F01_signatures=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1015 suspectscore=0 mlxlogscore=996 spamscore=0 mlxscore=0 phishscore=0 bulkscore=0 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103310144 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The clkgen-pll driver now embed the clock names (assuming the right compatible is used). Remove all clock-output-names property and update when necessary the compatible. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard --- arch/arm/boot/dts/stih407-clock.dtsi | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index ecd568777e5f..2603226a6ca8 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -36,8 +36,6 @@ compatible = "st,stih407-clkgen-plla9"; clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; }; }; @@ -74,12 +72,9 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,clkgen-pll0"; + compatible = "st,clkgen-pll0-a0"; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; - clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ }; clk_s_a0_flexgen: clk-s-a0-flexgen { @@ -112,21 +107,16 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,clkgen-pll0"; + compatible = "st,clkgen-pll0-c0"; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll0-odf-0"; - clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ }; clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,clkgen-pll1"; + compatible = "st,clkgen-pll1-c0"; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll1-odf-0"; }; clk_s_c0_flexgen: clk-s-c0-flexgen {