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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id p5sm1950179lfg.183.2021.04.19.15.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Apr 2021 15:51:45 -0700 (PDT) From: Linus Walleij To: netdev@vger.kernel.org, "David S . Miller" , Jakub Kicinski Cc: Linus Walleij , Zoltan HERPAI , Raylynn Knight , devicetree@vger.kernel.org Subject: [PATCH 1/3] net: ethernet: ixp4xx: Add DT bindings Date: Tue, 20 Apr 2021 00:51:31 +0200 Message-Id: <20210419225133.2005360-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the IXP4xx ethernet controller with optional MDIO bridge. Cc: Zoltan HERPAI Cc: Raylynn Knight Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Add schema for the (optional) embedded MDIO bus inside the ethernet controller in an "mdio" node instead of just letting the code randomly populate and present it to the operating system. - Reference the standard schemas for ethernet controller and MDIO buses. - Add intel,npe to indentify the NPE unit used with each ethernet adapter. --- .../bindings/net/intel,ixp4xx-ethernet.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/intel,ixp4xx-ethernet.yaml -- 2.29.2 diff --git a/Documentation/devicetree/bindings/net/intel,ixp4xx-ethernet.yaml b/Documentation/devicetree/bindings/net/intel,ixp4xx-ethernet.yaml new file mode 100644 index 000000000000..55ef6ff7d171 --- /dev/null +++ b/Documentation/devicetree/bindings/net/intel,ixp4xx-ethernet.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx ethernet + +allOf: + - $ref: "ethernet-controller.yaml#" + +maintainers: + - Linus Walleij + +description: | + The Intel IXP4xx ethernet makes use of the IXP4xx NPE (Network + Processing Engine) and the IXP4xx Queue Mangager to process + the ethernet frames. It can optionally contain an MDIO bus to + talk to PHYs. + +properties: + compatible: + const: intel,ixp4xx-ethernet + + reg: + maxItems: 1 + description: Ethernet MMIO address range + + queue-rx: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: phandle to the RX queue on the NPE + + queue-txready: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: phandle to the TX READY queue on the NPE + + phy-handle: true + + intel,npe: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + description: which NPE (Network Processing Engine) this ethernet + instance is using + + mdio: + type: object + $ref: "mdio.yaml#" + description: optional node for embedded MDIO controller + +required: + - compatible + - reg + - queue-rx + - queue-txready + +additionalProperties: false + +examples: + - | + ethernet@c8009000 { + compatible = "intel,ixp4xx-ethernet"; + reg = <0xc8009000 0x1000>; + status = "disabled"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + intel,npe = <1>; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy1: phy@1 { + #phy-cells = <0>; + reg = <1>; + }; + }; + };