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[83.51.243.231]) by smtp.gmail.com with ESMTPSA id u5sm3642433wrt.38.2021.05.06.04.15.35 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 May 2021 04:15:35 -0700 (PDT) From: Sergio Paracuellos To: vkoul@kernel.org Cc: linux-phy@lists.infradead.org, kishon@ti.com, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, gregkh@linuxfoundation.org, neil@brown.name, ilya.lipnitskiy@gmail.com Subject: [PATCH 2/5] dt-bindings: phy: mediatek, mt7621-pci-phy: add clock entries Date: Thu, 6 May 2021 13:15:28 +0200 Message-Id: <20210506111531.21978-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506111531.21978-1-sergio.paracuellos@gmail.com> References: <20210506111531.21978-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' Hence update schema with the add of the entries related to clock. Signed-off-by: Sergio Paracuellos --- .../bindings/phy/mediatek,mt7621-pci-phy.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml index 0ccaded3f245..d8614ef8995c 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml @@ -16,6 +16,14 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + description: + PHY reference clock. Must contain an entry in clock-names. + + clock-names: + const: sys_clk + "#phy-cells": const: 1 description: selects if the phy is dual-ported @@ -23,6 +31,8 @@ properties: required: - compatible - reg + - clocks + - clock-names - "#phy-cells" additionalProperties: false @@ -32,5 +42,7 @@ examples: pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; + clocks = <&sysc 0>; + clock-names = "sys_clk"; #phy-cells = <1>; };