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Wed, 12 May 2021 05:51:01 -0700 Envelope-to: git@xilinx.com, robh+dt@kernel.org, mdf@kernel.org, trix@redhat.com, arnd@arndb.de, gregkh@linuxfoundation.org, zou_wei@huawei.com, iwamatsu@nigauri.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org, chinnikishore369@gmail.com Received: from [10.140.6.60] (port=37340 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lgoKJ-0002rt-Do; Wed, 12 May 2021 05:50:59 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 1/4] drivers: firmware: Add PDI load API support Date: Wed, 12 May 2021 18:20:39 +0530 Message-ID: <20210512125042.30973-2-nava.manne@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210512125042.30973-1-nava.manne@xilinx.com> References: <20210512125042.30973-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 20c7cec3-df7c-4b2b-a116-08d91544a511 X-MS-TrafficTypeDiagnostic: DM6PR02MB6252: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:644; 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CAT:NONE; SFS:(4636009)(39860400002)(396003)(346002)(376002)(136003)(36840700001)(46966006)(8676002)(8936002)(5660300002)(82310400003)(478600001)(7696005)(110136005)(70206006)(921005)(26005)(70586007)(36906005)(316002)(7636003)(2906002)(426003)(7416002)(1076003)(6666004)(83380400001)(336012)(2616005)(36860700001)(9786002)(47076005)(36756003)(82740400003)(356005)(186003)(102446001)(83996005)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2021 12:51:22.0101 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20c7cec3-df7c-4b2b-a116-08d91544a511 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT041.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6252 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds load PDI API support to enable full/partial PDI loading from linux. Programmable Device Image (PDI) is combination of headers, images and bitstream files to be loaded. Signed-off-by: Nava kishore Manne --- Changes for v2: -Updated API Doc and commit msg. No functional changes. Changes for v3: -None. Changes for v4: -Rebased the changes on linux-next. No functional changes Changes for v5: -None. drivers/firmware/xilinx/zynqmp.c | 17 +++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 10 ++++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 15b138326ecc..2db571da9ad8 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -1011,6 +1011,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, } EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement); +/** + * zynqmp_pm_load_pdi - Load and process PDI + * @src: Source device where PDI is located + * @address: PDI src address + * + * This function provides support to load PDI from linux + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_load_pdi(const u32 src, const u64 address) +{ + return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src, + lower_32_bits(address), + upper_32_bits(address), 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi); + /** * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using * AES-GCM core. diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 9d1a5c175065..56b426fe020c 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -52,6 +52,10 @@ #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U +/* Loader commands */ +#define PM_LOAD_PDI 0x701 +#define PDI_SRC_DDR 0xF + /* * Firmware FPGA Manager flags * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration @@ -411,6 +415,7 @@ int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, u32 *value); int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, u32 value); +int zynqmp_pm_load_pdi(const u32 src, const u64 address); #else static inline int zynqmp_pm_get_api_version(u32 *version) { @@ -622,6 +627,11 @@ static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, { return -ENODEV; } + +static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */