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Thu, 27 May 2021 17:52:44 -0700 Envelope-to: mdf@kernel.org, robh@kernel.org, trix@redhat.com, devicetree@vger.kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.19.73.109] (port=34032 helo=xsj-xw9400.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lmQk0-0007Ia-2p; Thu, 27 May 2021 17:52:44 -0700 Received: by xsj-xw9400.xilinx.com (Postfix, from userid 21952) id E9EF66032AF; Thu, 27 May 2021 17:50:06 -0700 (PDT) From: Lizhi Hou To: CC: Lizhi Hou , , , , , , , , , , , Max Zhen Subject: [PATCH V7 XRT Alveo 13/20] fpga: xrt: User Clock Subsystem driver Date: Thu, 27 May 2021 17:49:52 -0700 Message-ID: <20210528004959.61354-14-lizhi.hou@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210528004959.61354-1-lizhi.hou@xilinx.com> References: <20210528004959.61354-1-lizhi.hou@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1e6fb282-7c51-4c26-3302-08d92172ef13 X-MS-TrafficTypeDiagnostic: DM6PR02MB6396: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2399; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 00:52:56.9827 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e6fb282-7c51-4c26-3302-08d92172ef13 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0056.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6396 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add User Clock Subsystem (UCS) driver. UCS is a hardware function discovered by walking xclbin metadata. A xrt device node will be created for it. UCS enables/disables the dynamic region clocks. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reviewed-by: Tom Rix --- drivers/fpga/xrt/lib/xleaf/ucs.c | 152 +++++++++++++++++++++++++++++++ 1 file changed, 152 insertions(+) create mode 100644 drivers/fpga/xrt/lib/xleaf/ucs.c diff --git a/drivers/fpga/xrt/lib/xleaf/ucs.c b/drivers/fpga/xrt/lib/xleaf/ucs.c new file mode 100644 index 000000000000..a7a96ddde44f --- /dev/null +++ b/drivers/fpga/xrt/lib/xleaf/ucs.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo FPGA UCS Driver + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#include +#include +#include +#include +#include +#include "metadata.h" +#include "xleaf.h" +#include "xleaf/clock.h" + +#define UCS_ERR(ucs, fmt, arg...) \ + xrt_err((ucs)->xdev, fmt "\n", ##arg) +#define UCS_WARN(ucs, fmt, arg...) \ + xrt_warn((ucs)->xdev, fmt "\n", ##arg) +#define UCS_INFO(ucs, fmt, arg...) \ + xrt_info((ucs)->xdev, fmt "\n", ##arg) +#define UCS_DBG(ucs, fmt, arg...) \ + xrt_dbg((ucs)->xdev, fmt "\n", ##arg) + +#define XRT_UCS "xrt_ucs" + +#define XRT_UCS_CHANNEL1_REG 0 +#define XRT_UCS_CHANNEL2_REG 8 + +#define CLK_MAX_VALUE 6400 + +XRT_DEFINE_REGMAP_CONFIG(ucs_regmap_config); + +struct xrt_ucs { + struct xrt_device *xdev; + struct regmap *regmap; + struct mutex ucs_lock; /* ucs dev lock */ +}; + +static void xrt_ucs_event_cb(struct xrt_device *xdev, void *arg) +{ + struct xrt_event *evt = (struct xrt_event *)arg; + enum xrt_events e = evt->xe_evt; + struct xrt_device *leaf; + enum xrt_subdev_id id; + int instance; + + id = evt->xe_subdev.xevt_subdev_id; + instance = evt->xe_subdev.xevt_subdev_instance; + + if (e != XRT_EVENT_POST_CREATION) { + xrt_dbg(xdev, "ignored event %d", e); + return; + } + + if (id != XRT_SUBDEV_CLOCK) + return; + + leaf = xleaf_get_leaf_by_id(xdev, XRT_SUBDEV_CLOCK, instance); + if (!leaf) { + xrt_err(xdev, "does not get clock subdev"); + return; + } + + xleaf_call(leaf, XRT_CLOCK_VERIFY, NULL); + xleaf_put_leaf(xdev, leaf); +} + +static int ucs_enable(struct xrt_ucs *ucs) +{ + int ret; + + mutex_lock(&ucs->ucs_lock); + ret = regmap_write(ucs->regmap, XRT_UCS_CHANNEL2_REG, 1); + mutex_unlock(&ucs->ucs_lock); + + return ret; +} + +static int +xrt_ucs_leaf_call(struct xrt_device *xdev, u32 cmd, void *arg) +{ + switch (cmd) { + case XRT_XLEAF_EVENT: + xrt_ucs_event_cb(xdev, arg); + break; + default: + xrt_err(xdev, "unsupported cmd %d", cmd); + return -EINVAL; + } + + return 0; +} + +static int ucs_probe(struct xrt_device *xdev) +{ + struct xrt_ucs *ucs = NULL; + void __iomem *base = NULL; + struct resource *res; + + ucs = devm_kzalloc(&xdev->dev, sizeof(*ucs), GFP_KERNEL); + if (!ucs) + return -ENOMEM; + + xrt_set_drvdata(xdev, ucs); + ucs->xdev = xdev; + mutex_init(&ucs->ucs_lock); + + res = xrt_get_resource(xdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + base = devm_ioremap_resource(&xdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + ucs->regmap = devm_regmap_init_mmio(&xdev->dev, base, &ucs_regmap_config); + if (IS_ERR(ucs->regmap)) { + UCS_ERR(ucs, "map base %pR failed", res); + return PTR_ERR(ucs->regmap); + } + ucs_enable(ucs); + + return 0; +} + +static struct xrt_dev_endpoints xrt_ucs_endpoints[] = { + { + .xse_names = (struct xrt_dev_ep_names[]) { + { .ep_name = XRT_MD_NODE_UCS_CONTROL_STATUS }, + { NULL }, + }, + .xse_min_ep = 1, + }, + { 0 }, +}; + +static struct xrt_driver xrt_ucs_driver = { + .driver = { + .name = XRT_UCS, + }, + .subdev_id = XRT_SUBDEV_UCS, + .endpoints = xrt_ucs_endpoints, + .probe = ucs_probe, + .leaf_call = xrt_ucs_leaf_call, +}; + +XRT_LEAF_INIT_FINI_FUNC(ucs);