From patchwork Thu Jun 10 08:20:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 458016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05D1CC48BCD for ; Thu, 10 Jun 2021 08:21:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E936161406 for ; Thu, 10 Jun 2021 08:21:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230288AbhFJIW6 (ORCPT ); Thu, 10 Jun 2021 04:22:58 -0400 Received: from relay7-d.mail.gandi.net ([217.70.183.200]:55703 "EHLO relay7-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230264AbhFJIW4 (ORCPT ); Thu, 10 Jun 2021 04:22:56 -0400 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay7-d.mail.gandi.net (Postfix) with ESMTPSA id 343A220006; Thu, 10 Jun 2021 08:20:58 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , , Rob Herring , , Krzysztof Kozlowski Cc: Michal Simek , Naga Sureshkumar Relli , Amit Kumar Mahapatra , Thomas Petazzoni , , , helmut.grohne@intenta.de, Srinivas Goud , Siva Durga Prasad Paladugu , Miquel Raynal Subject: [PATCH v23 08/18] dt-binding: memory: pl353-smc: Enhance the description of the reg property Date: Thu, 10 Jun 2021 10:20:30 +0200 Message-Id: <20210610082040.2075611-9-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210610082040.2075611-1-miquel.raynal@bootlin.com> References: <20210610082040.2075611-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SMC bus controller features several register sets. The one pointed by the reg property is for the SMC configuration (impacts the sub-controllers configuration), while the others are meant to be used to send regular cycles on the memory bus (eg. CMD, ADDR, DATA for a NAND device). Detail this a little bit for the sake of clarity. Signed-off-by: Miquel Raynal --- .../devicetree/bindings/memory-controllers/pl353-smc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt index ecd46856f139..ba6a5426f62b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt @@ -5,7 +5,8 @@ of memory interfaces: NAND and memory mapped interfaces (such as SRAM or NOR). Required properties: - compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell". -- reg : Controller registers map and length. +- reg : SMC controller and sub-controllers configuration + registers. - clock-names : List of input clock names - "memclk", "apb_pclk" (See clock bindings for details). - clocks : Clock phandles (see clock bindings for details).