| Message ID | 20210612160422.330705-5-anup.patel@wdc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISC-V ACLINT Support | expand |
On Sat, 12 Jun 2021 17:04:16 +0100, Anup Patel <anup.patel@wdc.com> wrote: > > If IPI calls are injected using SBI IPI calls then remote TLB flush > using SBI RFENCE calls is much faster because using IPIs for remote > TLB flush would still endup as SBI IPI calls with extra processing > on kernel side. > > It is now possible to have specialized hardware (such as RISC-V AIA) > which allows S-mode software to directly inject IPIs without any > assistance from M-mode runtime firmware. > > This patch extends remote TLB flush functions to use IPIs whenever > underlying IPI operations are suitable for remote FENCEs. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > --- > arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++--------- > 1 file changed, 48 insertions(+), 14 deletions(-) > > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > index 720b443c4528..009c56fa102d 100644 > --- a/arch/riscv/mm/tlbflush.c > +++ b/arch/riscv/mm/tlbflush.c > @@ -1,39 +1,73 @@ > // SPDX-License-Identifier: GPL-2.0 > +/* > + * TLB flush implementation. > + * > + * Copyright (c) 2021 Western Digital Corporation or its affiliates. > + */ I find this a bit odd. You don't mention this addition in the commit message, and a quick look at the commits touching tlbflush.[ch] doesn't make the copyright assignment obvious (most commits originate from either SiFive or Christoph). In any way, please keep this kind of changes out of this series if possible, and have a separate discussion on who gets to brag about this code. Thanks, M. -- Without deviation from the norm, progress is not possible.
On Sun, Jun 13, 2021 at 3:03 PM Marc Zyngier <maz@kernel.org> wrote: > > On Sat, 12 Jun 2021 17:04:16 +0100, > Anup Patel <anup.patel@wdc.com> wrote: > > > > If IPI calls are injected using SBI IPI calls then remote TLB flush > > using SBI RFENCE calls is much faster because using IPIs for remote > > TLB flush would still endup as SBI IPI calls with extra processing > > on kernel side. > > > > It is now possible to have specialized hardware (such as RISC-V AIA) > > which allows S-mode software to directly inject IPIs without any > > assistance from M-mode runtime firmware. > > > > This patch extends remote TLB flush functions to use IPIs whenever > > underlying IPI operations are suitable for remote FENCEs. > > > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > --- > > arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++--------- > > 1 file changed, 48 insertions(+), 14 deletions(-) > > > > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c > > index 720b443c4528..009c56fa102d 100644 > > --- a/arch/riscv/mm/tlbflush.c > > +++ b/arch/riscv/mm/tlbflush.c > > @@ -1,39 +1,73 @@ > > // SPDX-License-Identifier: GPL-2.0 > > +/* > > + * TLB flush implementation. > > + * > > + * Copyright (c) 2021 Western Digital Corporation or its affiliates. > > + */ > > I find this a bit odd. You don't mention this addition in the commit > message, and a quick look at the commits touching tlbflush.[ch] > doesn't make the copyright assignment obvious (most commits originate > from either SiFive or Christoph). > > In any way, please keep this kind of changes out of this series if > possible, and have a separate discussion on who gets to brag about > this code. I agree it's unrelated change. The commit history suggest mm/tlbflush.c was added by Christoph and other commits after that are from Atish (Western Digital). I will sort this out separately. Regards, Anup > > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible.
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 720b443c4528..009c56fa102d 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -1,39 +1,73 @@ // SPDX-License-Identifier: GPL-2.0 +/* + * TLB flush implementation. + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ #include <linux/mm.h> #include <linux/smp.h> #include <linux/sched.h> #include <asm/sbi.h> +static void ipi_flush_tlb_all(void *info) +{ + local_flush_tlb_all(); +} + void flush_tlb_all(void) { - sbi_remote_sfence_vma(NULL, 0, -1); + if (!riscv_use_ipi_for_rfence()) + sbi_remote_sfence_vma(NULL, 0, -1); + else + on_each_cpu(ipi_flush_tlb_all, NULL, 1); +} + +struct flush_range_data { + unsigned long start; + unsigned long size; +}; + +static void ipi_flush_range(void *info) +{ + struct flush_range_data *data = info; + + /* local cpu is the only cpu present in cpumask */ + if (data->size <= PAGE_SIZE) + local_flush_tlb_page(data->start); + else + local_flush_tlb_all(); } /* - * This function must not be called with cmask being null. + * This function must not be called with NULL cpumask. * Kernel may panic if cmask is NULL. */ -static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start, - unsigned long size) +static void flush_range(struct cpumask *cmask, unsigned long start, + unsigned long size) { + struct flush_range_data info; struct cpumask hmask; unsigned int cpuid; if (cpumask_empty(cmask)) return; + info.start = start; + info.size = size; + cpuid = get_cpu(); if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) { - /* local cpu is the only cpu present in cpumask */ - if (size <= PAGE_SIZE) - local_flush_tlb_page(start); - else - local_flush_tlb_all(); + ipi_flush_range(&info); } else { - riscv_cpuid_to_hartid_mask(cmask, &hmask); - sbi_remote_sfence_vma(cpumask_bits(&hmask), start, size); + if (!riscv_use_ipi_for_rfence()) { + riscv_cpuid_to_hartid_mask(cmask, &hmask); + sbi_remote_sfence_vma(cpumask_bits(&hmask), + start, size); + } else { + on_each_cpu_mask(cmask, ipi_flush_range, &info, 1); + } } put_cpu(); @@ -41,16 +75,16 @@ static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start, void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm_cpumask(mm), 0, -1); + flush_range(mm_cpumask(mm), 0, -1); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); + flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE); } void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start); + flush_range(mm_cpumask(vma->vm_mm), start, end - start); }
If IPI calls are injected using SBI IPI calls then remote TLB flush using SBI RFENCE calls is much faster because using IPIs for remote TLB flush would still endup as SBI IPI calls with extra processing on kernel side. It is now possible to have specialized hardware (such as RISC-V AIA) which allows S-mode software to directly inject IPIs without any assistance from M-mode runtime firmware. This patch extends remote TLB flush functions to use IPIs whenever underlying IPI operations are suitable for remote FENCEs. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 14 deletions(-)