From patchwork Tue Jun 15 17:32:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2771C48BDF for ; Tue, 15 Jun 2021 17:33:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C2D7F6144E for ; Tue, 15 Jun 2021 17:33:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231468AbhFORfK (ORCPT ); Tue, 15 Jun 2021 13:35:10 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35329 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231262AbhFORe6 (ORCPT ); Tue, 15 Jun 2021 13:34:58 -0400 X-UUID: 38ef2d217b464496a555ce6007250263-20210616 X-UUID: 38ef2d217b464496a555ce6007250263-20210616 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 907989659; Wed, 16 Jun 2021 01:32:46 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:45 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Jason-JH Lin Subject: [PATCH 16/27] arm64: dts: mt8195: add display node Date: Wed, 16 Jun 2021 01:32:22 +0800 Message-ID: <20210615173233.26682-16-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jason-JH Lin add display node. Signed-off-by: Jason-JH Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 76 ++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 856b0e938009..f362288ad828 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1911,6 +1911,82 @@ #clock-cells = <1>; }; + vdosys_config@1c01a000 { + compatible = "mediatek,mt8195-vdosys"; + reg = <0 0x1c01a000 0 0x1000>; + reg-names = "vdosys0_config"; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + mutex: disp_mutex0@1c016000 { + compatible = "mediatek,mt8195-disp-mutex"; + reg = <0 0x1c016000 0 0x1000>; + reg-names = "vdo0_mutex"; + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clock-names = "vdo0_mutex"; + interrupts = ; + }; + + ovl0: disp_ovl@1c000000 { + compatible = "mediatek,mt8195-disp-ovl"; + reg = <0 0x1c000000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; + }; + + rdma0: disp_rdma@1c002000 { + compatible = "mediatek,mt8195-disp-rdma"; + reg = <0 0x1c002000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; + }; + + color0: disp_color@1c003000 { + compatible = "mediatek,mt8195-disp-color"; + reg = <0 0x1c003000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + ccorr0: disp_ccorr@1c004000 { + compatible = "mediatek,mt8195-disp-ccorr"; + reg = <0 0x1c004000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + aal0: disp_aal@1c005000 { + compatible = "mediatek,mt8195-disp-aal"; + reg = <0 0x1c005000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + gamma0: disp_gamma@1c006000 { + compatible = "mediatek,mt8195-disp-gamma"; + reg = <0 0x1c006000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + dither0: disp_dither@1c007000 { + compatible = "mediatek,mt8195-disp-dither"; + reg = <0 0x1c007000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + smi_common0: smi@1c01b000 { compatible = "mediatek,mt8195-smi-common"; mediatek,common-id = <0>;