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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id t17sm440430ljk.102.2021.07.31.14.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 14:38:30 -0700 (PDT) From: Linus Walleij To: Jens Axboe , linux-ide@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 4/5 v2] pata: ixp4xx: Add DT bindings Date: Sat, 31 Jul 2021 23:35:54 +0200 Message-Id: <20210731213555.2965356-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210731213555.2965356-1-linus.walleij@linaro.org> References: <20210731213555.2965356-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Intel IXP4xx compact flash card interface. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Itemize the registers - Drop the epansion bus set-up to alleviate warnings --- .../ata/intel,ixp4xx-compact-flash.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml -- 2.31.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml b/Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml new file mode 100644 index 000000000000..52e18600ecff --- /dev/null +++ b/Documentation/devicetree/bindings/ata/intel,ixp4xx-compact-flash.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/intel,ixp4xx-compact-flash.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx CompactFlash Card Controller + +maintainers: + - Linus Walleij + +description: | + The IXP4xx network processors have a CompactFlash interface that presents + a CompactFlash card to the system as a true IDE (parallel ATA) device. The + device is always connected to the expansion bus of the IXP4xx SoCs using one + or two chip select areas and address translating logic on the board. The + node must be placed inside a chip select node on the IXP4xx expansion bus. + +properties: + compatible: + const: intel,ixp4xx-compact-flash + + reg: + items: + - description: Command interface registers + - description: Control interface registers + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: pata-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + bus@c4000000 { + compatible = "intel,ixp43x-expansion-bus-controller", "syscon"; + reg = <0xc4000000 0x1000>; + native-endian; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>; + dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>; + ide@1,0 { + compatible = "intel,ixp4xx-compact-flash"; + reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>; + interrupt-parent = <&gpio0>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + }; + }; + +...