From patchwork Thu Aug 26 12:38:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yifeng Zhao X-Patchwork-Id: 503005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A2AFC4320E for ; Thu, 26 Aug 2021 12:39:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 48A9D610A4 for ; Thu, 26 Aug 2021 12:39:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242277AbhHZMjs (ORCPT ); Thu, 26 Aug 2021 08:39:48 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:60058 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241129AbhHZMjr (ORCPT ); Thu, 26 Aug 2021 08:39:47 -0400 Received: from localhost (unknown [192.168.167.235]) by lucky1.263xmail.com (Postfix) with ESMTP id 69BEBD731C; Thu, 26 Aug 2021 20:38:53 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-SKE-CHECKED: 1 X-ANTISPAM-LEVEL: 2 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P32763T139761010153216S1629981525980003_; Thu, 26 Aug 2021 20:38:53 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <5edbae06160058b9826b59ee43e0d716> X-RL-SENDER: yifeng.zhao@rock-chips.com X-SENDER: zyf@rock-chips.com X-LOGIN-NAME: yifeng.zhao@rock-chips.com X-FST-TO: heiko@sntech.de X-RCPT-COUNT: 12 X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-System-Flag: 0 From: Yifeng Zhao To: heiko@sntech.de, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, vkoul@kernel.org, michael.riesch@wolfvision.net, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, kishon@ti.com, p.zabel@pengutronix.de, Yifeng Zhao Subject: [PATCH v1 3/3] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 Date: Thu, 26 Aug 2021 20:38:44 +0800 Message-Id: <20210826123844.8464-4-yifeng.zhao@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210826123844.8464-1-yifeng.zhao@rock-chips.com> References: <20210826123844.8464-1-yifeng.zhao@rock-chips.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the core dt-node for the rk3568's naneng combo phys. Signed-off-by: Yifeng Zhao --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index d89831bee1eb..b421e3d52412 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -214,11 +214,31 @@ }; }; + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipegrf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + grf: syscon@fdc60000 { compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; reg = <0x0 0xfdc60000 0x0 0x10000>; }; + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; @@ -862,6 +882,54 @@ status = "disabled"; }; + combphy0_us: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + status = "disabled"; + }; + + combphy1_usq: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + status = "disabled"; + }; + + combphy2_psq: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>;