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[23.128.96.18]) by mx.google.com with ESMTP id u12si10607783lfs.194.2021.09.14.08.56.14; Tue, 14 Sep 2021 08:56:14 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="xH/7ymzM"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234180AbhINP5a (ORCPT + 6 others); Tue, 14 Sep 2021 11:57:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231928AbhINP53 (ORCPT ); Tue, 14 Sep 2021 11:57:29 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FCD7C061574 for ; Tue, 14 Sep 2021 08:56:12 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id q21so24827778ljj.6 for ; Tue, 14 Sep 2021 08:56:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q4orUGhIY8AIL0IaUBN0v2F6x+wP94qlQUHr4gzQ1HY=; b=xH/7ymzMCA4XcMiCojiw0g6bs54GiLlLySMqIyU/azwTgDlDc8dm1BM5B3ZtNofVZy CtlruqKxsj7Q4XODxjwk6CTBW58RKIYGTprrnYClD75XzK+fv/kFilw5nhIxVlJRhg3q ChAtMDKJ1ZfcawdBVGfyk0vyPlghG2sysom3cRHLHKYG9M52CCTNmZ9yS0g//VHLCOQ/ IGLc6otc/Hqp0+lyyE22anuVBfcT5/m1z8LHgD4xfejk7CQzwY2z7UWPSRbmTck9qYsZ A2NQkvqd4uQOmdhiyKxfDlThhUQbxTP+aOnEcm7Gw6oLxuGAwdBdptuiMz5Ptkr2nEe7 mmHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q4orUGhIY8AIL0IaUBN0v2F6x+wP94qlQUHr4gzQ1HY=; b=eXR1FCuMLvUbMk05AUxgqRx4HMvwJO+Wc3Wg8ZYXXEcbGp64tjBftH04F0ST0F11ih OzVIiru5kYPEHL9GqGFK6hw6+vCaYBSz0/GxWAOf4G9zbWLnMcERaUU1N2M1ZITEOuxv L3+j/6iZEFSmsRrYtcEVJ8J2CQuQLrVTChzHOKatGZVYG0Oq74QEsqbt+t+jNB2wDCvr CQZk+qojMznEF7WOCSh8pYfu45u5mg+fil0UUYr4ypuvwrE3cjZ544IT5m7LmXqbbXOl eS6r/OqS/FD670njTbiyPwSllbvnHJSM7tcLNrgUaQQ9ASFTbIr87S4kaFlICn+/I8xV 1r1w== X-Gm-Message-State: AOAM533LXDLAyIKnruNjhL0kV4ELdXT/ztXP16WZhq3wD0IvRlyyKJMx ho1F7XMfC4oFbjzDEmZRX//6dAufsBjetqq9 X-Received: by 2002:a2e:a4ad:: with SMTP id g13mr16112113ljm.391.1631634970657; Tue, 14 Sep 2021 08:56:10 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id b20sm1151951lfc.75.2021.09.14.08.56.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Sep 2021 08:56:09 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , =?utf-8?q?Pawe=C5=82_Chmiel?= , Chanwoo Choi , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette Cc: Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 1/6] clk: samsung: Enable bus clock on init Date: Tue, 14 Sep 2021 18:56:02 +0300 Message-Id: <20210914155607.14122-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210914155607.14122-1-semen.protsenko@linaro.org> References: <20210914155607.14122-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org By default if bus clock has no users its "enable count" value is 0. It might be actually running if it's already enabled in bootloader, but then in some cases it can be disabled by mistake. For example, such case was observed when dw_mci_probe() enabled bus clock, then failed to do something and disabled that bus clock on error path. After that even attempt to read the 'clk_summary' file in DebugFS freezed forever, as CMU bus clock ended up being disabled and it wasn't possible to access CMU registers anymore. To avoid such cases, CMU driver must increment the ref count for that bus clock by running clk_prepare_enable(). There is already existing '.clk_name' field in struct samsung_cmu_info, exactly for that reason. It was added in commit 523d3de41f02 ("clk: samsung: exynos5433: Add support for runtime PM"). But the clock is actually enabled only in Exynos5433 clock driver. Let's mimic what is done there in generic samsung_cmu_register_one() function, so other drivers can benefit from that `.clk_name' field. As was described above, it might be helpful not only for PM reasons, but also to prevent possible erroneous clock gating on error paths. Another way to workaround that issue would be to use CLOCK_IS_CRITICAL flag for corresponding gate clocks. But that might be not very good design decision, as we might still want to disable that bus clock, e.g. on PM suspend. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.30.2 diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 1949ae7851b2..da65149fa502 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -357,6 +357,19 @@ struct samsung_clk_provider * __init samsung_cmu_register_one( ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids); + /* Keep bus clock running, so it's possible to access CMU registers */ + if (cmu->clk_name) { + struct clk *bus_clk; + + bus_clk = __clk_lookup(cmu->clk_name); + if (bus_clk) { + clk_prepare_enable(bus_clk); + } else { + pr_err("%s: could not find bus clock %s\n", __func__, + cmu->clk_name); + } + } + if (cmu->pll_clks) samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks, reg_base);