From patchwork Tue Dec 14 22:58:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 523751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D967EC433EF for ; Tue, 14 Dec 2021 22:59:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235105AbhLNW7G (ORCPT ); Tue, 14 Dec 2021 17:59:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235092AbhLNW7F (ORCPT ); Tue, 14 Dec 2021 17:59:05 -0500 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D69C9C06173F for ; Tue, 14 Dec 2021 14:59:04 -0800 (PST) Received: by mail-lf1-x133.google.com with SMTP id u3so39724066lfl.2 for ; Tue, 14 Dec 2021 14:59:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L4pIImixrdWMTKaYWRmzrWP1bf+OcXW6Av2PMVI53nk=; b=qyndXVPHUhhWwxY5Zzbkg3x5vUsiEK+u9FdWj8n7VtMK3HVs1hkf7hHqqOADZwZgOU BGobVzKnTnbZ0axjo9BbUVen8+6QfmwCUpEoGaeZjGlFV0PP5hDeFTmZnk/eIvL6Wkmo z+URfNuB9udJQW4r3OY+3W1pHYKadql3zEfKSXBe+yMqeuS9ofPvCbp2fSpbIe2A2SJx gGNCNWiGFCqPZqDwd+ZNJaHm+8x6zwXhJ2ubWYBrmSjD+HSaSU9Wa4fm9s0ETzOHP+1H Xm2aszqHgACWgA7qMmKM7co8Z0gy8bvykT42m7bPTlGteggnRu2Mscp3wvDwjg0qtpeA mnNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L4pIImixrdWMTKaYWRmzrWP1bf+OcXW6Av2PMVI53nk=; b=ipITjH6EZJzseh5hu6H07t5Wa6EPmSPOwAVwP3KRGiK4pLbIG5fEn3I7nSBej0dOCD vg67cPBag5mh3F9Xjuuf9Uxp7mB3R+ttXT06RAs+RMlObzyuvdEjjgi6CDyaEuJDMnDy Ez2XO6j+GtPxKKGPRdiGVv0E4Va6jwym8bl33dEt+yNcZ+NGfPptmk1cpkUGpLis1aI/ lwN+M1e6md4FGqkwWDrwyA1LHeHv9FCeXiRbOYC5PS76IJBtAfL85phmNivs8jRkgCoc kZrtBXxDpKeae0uI8tar2cdqwJKmtHej0xNIuZuD1m0/5nGekHg5YyXAkCB3yLOG5YK9 vCUQ== X-Gm-Message-State: AOAM531BsHOlATOWApezx1EKXefKrweFZjfsrGW/Hsi95FktdnbsMUOL zmhzao/u0h0BsjYizAZhvQ5tOQ== X-Google-Smtp-Source: ABdhPJyJXAvWYZFxmg3G09HUfR3xVYI4mAt3CKh5QbK0T+O/+Uzv1Df00bkHlb03AoXgbUQZfrZNGg== X-Received: by 2002:a05:6512:33a9:: with SMTP id i9mr7319218lfg.30.1639522743123; Tue, 14 Dec 2021 14:59:03 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id t10sm45115lja.105.2021.12.14.14.59.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Dec 2021 14:59:02 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v4 06/10] PCI: qcom: Add SM8450 PCIe support Date: Wed, 15 Dec 2021 01:58:42 +0300 Message-Id: <20211214225846.2043361-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211214225846.2043361-1-dmitry.baryshkov@linaro.org> References: <20211214225846.2043361-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On SM8450 platform PCIe hosts do not use all the clocks (and add several additional clocks), so expand the driver to handle these requirements. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 47 +++++++++++++++++++------- 1 file changed, 34 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2f9a9497733e..d129729bb2a6 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -161,7 +161,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[7]; + struct clk_bulk_data clks[9]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -195,7 +195,10 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; unsigned int pipe_clk_need_muxing:1; + unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; + unsigned int has_aggre0_clk:1; + unsigned int has_aggre1_clk:1; }; struct qcom_pcie { @@ -1146,6 +1149,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + unsigned int idx; int ret; res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); @@ -1159,18 +1163,22 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret) return ret; - res->clks[0].id = "aux"; - res->clks[1].id = "cfg"; - res->clks[2].id = "bus_master"; - res->clks[3].id = "bus_slave"; - res->clks[4].id = "slave_q2a"; - res->clks[5].id = "tbu"; - if (pcie->cfg->has_ddrss_sf_tbu_clk) { - res->clks[6].id = "ddrss_sf_tbu"; - res->num_clks = 7; - } else { - res->num_clks = 6; - } + idx = 0; + res->clks[idx++].id = "aux"; + res->clks[idx++].id = "cfg"; + res->clks[idx++].id = "bus_master"; + res->clks[idx++].id = "bus_slave"; + res->clks[idx++].id = "slave_q2a"; + if (pcie->cfg->has_tbu_clk) + res->clks[idx++].id = "tbu"; + if (pcie->cfg->has_ddrss_sf_tbu_clk) + res->clks[idx++].id = "ddrss_sf_tbu"; + if (pcie->cfg->has_aggre0_clk) + res->clks[idx++].id = "aggre0"; + if (pcie->cfg->has_aggre1_clk) + res->clks[idx++].id = "aggre1"; + + res->num_clks = idx; ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) @@ -1509,15 +1517,27 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { static const struct qcom_pcie_cfg sdm845_cfg = { .ops = &ops_2_7_0, + .has_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8250_cfg = { .ops = &ops_1_9_0, + .has_tbu_clk = true, .has_ddrss_sf_tbu_clk = true, }; +/* Only for the PCIe0! */ +static const struct qcom_pcie_cfg sm8450_cfg = { + .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, + .pipe_clk_need_muxing = true, + .has_aggre0_clk = true, + .has_aggre1_clk = true, +}; + static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, + .has_tbu_clk = true, .pipe_clk_need_muxing = true, }; @@ -1625,6 +1645,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, + { .compatible = "qcom,pcie-sm8450", .data = &sm8450_cfg }, { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, { } };