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Tue, 21 Dec 2021 12:51:34 +0000 From: Sumit Gupta To: , , , , , CC: , , , , Subject: [Patch v3 4/9] arm64: tegra: Add node for CBB1.0 in Tegra194 SOC Date: Tue, 21 Dec 2021 18:21:12 +0530 Message-ID: <20211221125117.6545-5-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211221125117.6545-1-sumitg@nvidia.com> References: <20211221125117.6545-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2178e706-43cf-471f-b37f-08d9c480a0d2 X-MS-TrafficTypeDiagnostic: CY4PR1201MB0056:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: KmMSL7rIIiWk6Cb9fwfPa7dBvuENWX4JQfcTGXNGfGGkvZIv9IU0AmSkx9Xn/u7Y0kXdvdeaCx9fxUePGcxe/pzZjnxaDZ1VrebT0S58ONDjlPiJSvXM37thhT0tAtp4XcBUdA4CUO7iLOwcUsdwXLMk2hOnxsQwpjMItV+4f6TyoaRKwcydttoXjE33eClqGhK4pOczSDgKOHwysotNi0+gkmLdnTX8577QgQxBusM9u7DuVkbZiHWscPI7yMzRFIn0On+dB79JyxnRb46ATx/Os8HzT1PsomsHkwuhM2o2SXPtrRBuCacvLhLGDV9myNrpyTQybCQ5khqqW7yNPDk8T0S4+7zIL+y+2o8hub4xK2q0Vcv8zTA+HpoX4ILp2d9FCXFiKbWy6PALfbKHtdu/FAxpsMoRCLAdjjoHL5heJygWh+GMuuwDuZRRADa51Cb/DKR59eG/g5/6W8k9BRyb9kqve+9HL5PS1XcrC+M40pJ0TmUgPAI950Z+MUFLaKrxA32L0Vsf05gAnwHHMrwWdnt9UvMEmxfthM3BSxFl7RTDXkrxlSwkbAZ3WQXwAxq3yWJc3859J3YdbURPcY+Mx6KYL1wCbipm/53AV/F0mx7tWqfZTxNuQTE5FQ7N+wQEFBImuxTZ9X06mqsQMKE9zT2bWE317yBu04J010K/AvoR+cNXeGU/qfJhigErpifRahPvhRHGIcPnSyxiGuJfc7fhZJKYcTVx+i3Db73VHcmcv2ewAAarI7ze4vj19x992BohBvIIKivXBbaOER9XVC9wK+OJwpXX3EtYnotKo0QlXP+RuZyhDIgiqAIOEpdwCPubsUOJYqXyMSRiag== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(40470700002)(46966006)(36840700001)(5660300002)(40460700001)(26005)(4326008)(54906003)(316002)(8676002)(8936002)(70206006)(2906002)(107886003)(110136005)(186003)(6666004)(81166007)(36860700001)(36756003)(34020700004)(2616005)(336012)(86362001)(70586007)(47076005)(1076003)(83380400001)(7696005)(356005)(82310400004)(426003)(508600001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2021 12:51:38.1593 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2178e706-43cf-471f-b37f-08d9c480a0d2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB0056 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adding device tree nodes to enable the driver for handling errors from Control Backbone(CBB). CBB version 1.0 is used in Tegra194 SOC. Signed-off-by: Sumit Gupta --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 62 +++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 851e049b3519..dddc4982b35a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -22,7 +22,7 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x40000000>; - misc@100000 { + apbmisc: misc@100000 { compatible = "nvidia,tegra194-misc"; reg = <0x00100000 0xf000>, <0x0010f000 0x1000>; @@ -87,6 +87,27 @@ gpio-controller; }; + cbb-noc@2300000 { + compatible = "nvidia,tegra194-cbb-noc"; + reg = <0x02300000 0x1000>; + interrupts = , + ; + nvidia,axi2apb = <&axi2apb>; + nvidia,apbmisc = <&apbmisc>; + status = "okay"; + }; + + axi2apb: axi2apb@2390000 { + compatible = "nvidia,tegra194-axi2apb"; + reg = <0x2390000 0x1000>, + <0x23a0000 0x1000>, + <0x23b0000 0x1000>, + <0x23c0000 0x1000>, + <0x23d0000 0x1000>, + <0x23e0000 0x1000>; + status = "okay"; + }; + ethernet@2490000 { compatible = "nvidia,tegra194-eqos", "nvidia,tegra186-eqos", @@ -1359,6 +1380,26 @@ #phy-cells = <0>; }; + sce-noc@b600000 { + compatible = "nvidia,tegra194-sce-noc"; + reg = <0xb600000 0x1000>; + interrupts = , + ; + nvidia,axi2apb = <&axi2apb>; + nvidia,apbmisc = <&apbmisc>; + status = "okay"; + }; + + rce-noc@be00000 { + compatible = "nvidia,tegra194-rce-noc"; + reg = <0xbe00000 0x1000>; + interrupts = , + ; + nvidia,axi2apb = <&axi2apb>; + nvidia,apbmisc = <&apbmisc>; + status = "okay"; + }; + hsp_aon: hsp@c150000 { compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; reg = <0x0c150000 0x90000>; @@ -1374,6 +1415,15 @@ #mbox-cells = <2>; }; + aon-noc@c600000 { + compatible = "nvidia,tegra194-aon-noc"; + reg = <0xc600000 0x1000>; + interrupts = , + ; + nvidia,apbmisc = <&apbmisc>; + status = "okay"; + }; + gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0c240000 0x10000>; @@ -1552,6 +1602,16 @@ status = "okay"; }; + bpmp-noc@d600000 { + compatible = "nvidia,tegra194-bpmp-noc"; + reg = <0xd600000 0x1000>; + interrupts = , + ; + nvidia,axi2apb = <&axi2apb>; + nvidia,apbmisc = <&apbmisc>; + status = "okay"; + }; + host1x@13e00000 { compatible = "nvidia,tegra194-host1x"; reg = <0x13e00000 0x10000>,