Message ID | 20220318144534.17996-20-allen-kh.cheng@mediatek.com |
---|---|
State | Accepted |
Commit | 19c66219e4d5b813ebbd28621cfe9c450659ded7 |
Headers | show
Return-Path: <devicetree-owner@kernel.org> X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36C78C433EF for <linux-devicetree@archiver.kernel.org>; Fri, 18 Mar 2022 14:48:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234559AbiCROtt (ORCPT <rfc822;linux-devicetree@archiver.kernel.org>); Fri, 18 Mar 2022 10:49:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237635AbiCROry (ORCPT <rfc822;devicetree@vger.kernel.org>); Fri, 18 Mar 2022 10:47:54 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6ACFC2E8428; Fri, 18 Mar 2022 07:46:16 -0700 (PDT) X-UUID: 18cdfa03f7744090b743dcfdd5f1a3cc-20220318 X-UUID: 18cdfa03f7744090b743dcfdd5f1a3cc-20220318 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from <allen-kh.cheng@mediatek.com>) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1478199738; Fri, 18 Mar 2022 22:45:58 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 18 Mar 2022 22:45:57 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Mar 2022 22:45:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Mar 2022 22:45:56 +0800 From: Allen-KH Cheng <allen-kh.cheng@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> CC: <Project_Global_Chrome_Upstream_Group@mediatek.com>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, "Chen-Yu Tsai" <wenst@chromium.org>, Ryder Lee <ryder.lee@kernel.org>, Hui Liu <hui.liu@mediatek.com>, Allen-KH Cheng <allen-kh.cheng@mediatek.com> Subject: [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0 Date: Fri, 18 Mar 2022 22:45:31 +0800 Message-ID: <20220318144534.17996-20-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220318144534.17996-1-allen-kh.cheng@mediatek.com> References: <20220318144534.17996-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: <devicetree.vger.kernel.org> X-Mailing-List: devicetree@vger.kernel.org |
Series |
Add driver nodes for MT8192 SoC
|
expand
|
diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h index be9a7ca245b9..764ca9910fa9 100644 --- a/include/dt-bindings/reset/mt8192-resets.h +++ b/include/dt-bindings/reset/mt8192-resets.h @@ -27,4 +27,7 @@ #define MT8192_TOPRGU_SW_RST_NUM 23 +/* MMSYS resets */ +#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> --- include/dt-bindings/reset/mt8192-resets.h | 3 +++ 1 file changed, 3 insertions(+)