From patchwork Sat Mar 19 17:46:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 553049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A498C433FE for ; Sat, 19 Mar 2022 17:47:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243712AbiCSRsr (ORCPT ); Sat, 19 Mar 2022 13:48:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243805AbiCSRsm (ORCPT ); Sat, 19 Mar 2022 13:48:42 -0400 Received: from relay08.th.seeweb.it (relay08.th.seeweb.it [IPv6:2001:4b7a:2000:18::169]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BF2A247C29 for ; Sat, 19 Mar 2022 10:47:18 -0700 (PDT) Received: from localhost.localdomain (abxi119.neoplus.adsl.tpnet.pl [83.9.2.119]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 5DD053F64C; Sat, 19 Mar 2022 18:47:16 +0100 (CET) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/15] arm64: dts: qcom: msm8994: Add OCMEM node Date: Sat, 19 Mar 2022 18:46:42 +0100 Message-Id: <20220319174645.340379-13-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220319174645.340379-1-konrad.dybcio@somainline.org> References: <20220319174645.340379-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add OCMEM node to allow for GPU SRAM access. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/msm8994.dtsi | 17 +++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 1de1d9c4643d..92c1f87d6bba 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -24,6 +24,14 @@ &mmcc { <800000000>; }; +&ocmem { + reg = <0xfdd00000 0x2000>, <0xfec00000 0x100000>; + + gmu-sram@0 { + reg = <0x0 0x80000>; + }; +}; + &rpmcc { compatible = "qcom,rpmcc-msm8992"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index a2210cf9d0b4..2f531e93f3c6 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -1052,6 +1052,23 @@ mmcc: clock-controller@fd8c0000 { <960000000>, <600000000>; }; + + ocmem: ocmem@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x200000>; + reg-names = "ctrl", "mem"; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x180000>; + }; + }; }; timer: timer {