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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id i14-20020adfa50e000000b0020c5253d8c6sm6448105wrb.18.2022.05.01.12.26.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 12:26:32 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 3/8] riscv: dts: microchip: remove soc vendor from filenames Date: Sun, 1 May 2022 20:25:54 +0100 Message-Id: <20220501192557.2631936-4-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220501192557.2631936-1-mail@conchuod.ie> References: <20220501192557.2631936-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Having the SoC vendor both as the directory and in the filename adds little. Remove microchip from the filenames so that the files will resemble the other directories in riscv (and arm64). The new names follow a soc-board.dts & soc{,-fabric}.dtsi pattern. Signed-off-by: Conor Dooley Reviewed-by: Heiko Stuebner --- arch/riscv/boot/dts/microchip/Makefile | 2 +- .../microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} | 0 .../{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 2 +- .../riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} | 2 +- 4 files changed, 3 insertions(+), 3 deletions(-) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} (100%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (98%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (99%) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 855c1502d912..af3a5059b350 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi similarity index 100% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi rename to arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts similarity index 98% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index c71d6aa6137a..84b0015dfd47 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -3,7 +3,7 @@ /dts-v1/; -#include "microchip-mpfs.dtsi" +#include "mpfs.dtsi" /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi similarity index 99% rename from arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi rename to arch/riscv/boot/dts/microchip/mpfs.dtsi index bf21a2edd180..cc3386068c2d 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -3,7 +3,7 @@ /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" -#include "microchip-mpfs-fabric.dtsi" +#include "mpfs-fabric.dtsi" / { #address-cells = <2>;