From patchwork Sun May 1 19:25:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 568635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E1B0C433EF for ; Sun, 1 May 2022 19:26:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353403AbiEATaJ (ORCPT ); Sun, 1 May 2022 15:30:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353859AbiEATaH (ORCPT ); Sun, 1 May 2022 15:30:07 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C582C2CE07 for ; Sun, 1 May 2022 12:26:39 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id e24so17192979wrc.9 for ; Sun, 01 May 2022 12:26:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod-ie.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rfHaik7/2US1P/NFRRn4iUnlONPLqG6WILHOUefbBUo=; b=mVdv9kcwOOIpX2quM/vp3HTG42F5lFQfkJxhE6lBERhLVc7FEwAM/Tn4kD+7r62ie8 nvlAX46+VaiPTnF/vylOd4xI+lScf0samo6C4eeA/GEJ3KrbWWyOJe7OmoW+Vwii6HqG rWf8UXEHyGB2/s4ROjXXjewRBx1w/DyfWoz+chilBzG6ESM3ictgX6QuwAPWgZtrAMQt FBKns7Y1C/TbqWVRqL+8qkARg7ZrKNKNotJc+/nTWOdUs1fWwCOXM1WFnsji800uqj9Z YYMK7gooIH4sy+NV0qHp8CYytcOcOL/cVgfLYrvALtxEAKAJgLccYTYoodR9xMVbF2ES Y6vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rfHaik7/2US1P/NFRRn4iUnlONPLqG6WILHOUefbBUo=; b=PxIx0+8kNIUB/hq0r54v5bJVy/TwriSTL9QRTTSHyyAY7SeqrfB8ohDoyivYcHl9QT eMXaQ7FQdgmCVxMnmz8LVo8iyutxJyM0LD8DbpPxMkPIhNR+wztoRNW0QdY7s5qRufpM DooCYMl/eLMO5w4W/ED0+Jb+8U8aofhk93DLduF04FSu+FE6nH7sj+oOD045UlkzSwdH 1W5+O3sNLF4Kf83q7THjUyHn8ai2b7NrVRhUixqrtYTWpnep/uUP37khrKib8F7JlkXy fPQIGVa//Vc5zyinMSpR1nVOhvzkQJEE5suoJMWFr9t0SCvqyeSpIOU6U4uVb/oMzjuf 5Yog== X-Gm-Message-State: AOAM532kwR6gjZBZv7If8LNCmByMbIEFwdeYlCaU3SLRgzHmeqE9HfOc mM0qP7qc1XCRfpv2oiyd4HsMDQ== X-Google-Smtp-Source: ABdhPJx2i0mes1PmcgvFU5xWJ4TRUZY/DT1oIlVE5UY3f+NAzTWLdIkcmmjjxXaExuxvVcYoCFsCag== X-Received: by 2002:a5d:5012:0:b0:20a:d9a9:44dc with SMTP id e18-20020a5d5012000000b0020ad9a944dcmr7113624wrt.627.1651433198331; Sun, 01 May 2022 12:26:38 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id i14-20020adfa50e000000b0020c5253d8c6sm6448105wrb.18.2022.05.01.12.26.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 12:26:37 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 8/8] riscv: dts: microchip: add the sundance polarberry Date: Sun, 1 May 2022 20:25:59 +0100 Message-Id: <20220501192557.2631936-9-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220501192557.2631936-1-mail@conchuod.ie> References: <20220501192557.2631936-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add a minimal device tree for the PolarFire SoC based Sundance PolarBerry. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++ .../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++ 3 files changed, 112 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index af3a5059b350..39aae7b04f1c 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi new file mode 100644 index 000000000000..49380c428ec9 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts new file mode 100644 index 000000000000..96ec589d1571 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-polarberry-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Sundance PolarBerry"; + compatible = "sundance,polarberry", "microchip,mpfs"; + + aliases { + serial0 = &mmuart0; + ethernet0 = &mac1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x2e000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0xC0000000>; + status = "okay"; + }; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&mmuart0 { + status = "okay"; +}; + +&mmc { + status = "okay"; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&mac1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@5 { + reg = <5>; + ti,fifo-depth = <0x01>; + }; + phy0: ethernet-phy@4 { + reg = <4>; + ti,fifo-depth = <0x01>; + }; +}; + +&mac0 { + status = "disabled"; + phy-mode = "sgmii"; + phy-handle = <&phy0>; +}; + +&rtc { + status = "okay"; +}; + +&mbox { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +};