From patchwork Mon May 16 13:47:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 573097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 269D3C433F5 for ; Mon, 16 May 2022 13:48:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239892AbiEPNsZ (ORCPT ); Mon, 16 May 2022 09:48:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239914AbiEPNsU (ORCPT ); Mon, 16 May 2022 09:48:20 -0400 Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09D0139151; Mon, 16 May 2022 06:48:17 -0700 (PDT) Received: from toolbox.int.toradex.com ([81.221.85.15]) by mrelay.perfora.net (mreueus003 [74.208.5.2]) with ESMTPSA (Nemesis) id 0LlDCS-1nI54g2uZy-00b4hZ; Mon, 16 May 2022 15:48:01 +0200 From: Marcel Ziswiler To: linux-arm-kernel@lists.infradead.org Cc: Marcel Ziswiler , Fabio Estevam , Frank Rowand , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team , Rob Herring , Russell King , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/24] ARM: dts: imx7-colibri: add mdio phy node Date: Mon, 16 May 2022 15:47:12 +0200 Message-Id: <20220516134734.493065-3-marcel@ziswiler.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220516134734.493065-1-marcel@ziswiler.com> References: <20220516134734.493065-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:EiKg6GdRQXCI7+hpaiYbx3hOVFUyGIVPqTcXaERUXQ+xtiShetm DXtcaLGwYB8YcFjYLlFgKLC3CFKQ2ykja0a0hv4eu1mdhRNU7g5RoFeYuxoCjD4N8h8dxKN GjjrqNItnSsvS1t+Oenxgu+iy6d9PP0jnXm+ijLcCfqiFdiPwX/5dkXkbCs/CSjHTKAwKTh H5vXgiwtvmJdYeveJ+/HA== X-UI-Out-Filterresults: notjunk:1;V03:K0:ykcNnNnrMaM=:zNiM0tdeGuQynexErFVSWs +HoTlAhzM+vMPPT7ECRy+MMZ92doFs8SHFJsk2jaOg4rhM9XOGPZZ1hiZpeCq0yzsSDczqcSn Jj8hGGryhH/JAnrCte/DmjBg+phHQmZT1nC2n/Bsdrbz7LNdATQoWb6pmAmkf1m///6Bxketh KXJ//nhk7BcnFE7dlhMTxdfq4478Rtr38sipuzQb0rLytAUDqPr5KnIzngdXas9mReHbdUsKs 3JPFrp9xlt7+SsyC6uwhyLzSueVmvatmGYiuSz2FVkNu++KzoyEkiT/1kzukqQiMy9omPPmWe wwZ7DICVP+jXyc6J7LX8sUzL8ROqutpke2dnkNErZ9kyLGJdxwcqswvA4m4x3Ev6kmDAw+z2L Mwz3iNw2SA5SPX2qxVnGZltH3rBwQXfHv1EIqzVsoy1v3Y3I+ZWA7qAsluQBtgtqosW3QjEIB J4ueNeNeNMPLXgie5Q/xEL5z5QmoB0YUmcQF6zHi/6cLfQVMJX0kOWvm0hWar/dvHC3i15UbO EQP2ml+KPuHBfrkRDPuQixbf42jUMwS/MNTlemg8pm4urfbE9l+kL2nk+z1PLFHIzxaQbL0AH G0QSOQDljBwyAESvEZm/WuW5M/XIA4hBh9cCsgYqkPkzLenq98irLYd6YeUc7x5WDYUqhMrq2 arSTs4iPogxglWECtG4ydEiFppP6cb9ahA707Vs/CYOqnXRsyv/QTbf5TxjeNsuhiTCU= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Marcel Ziswiler Add the MDIO bus with the respective PHY to allow for making changes to that easier. While at it also alphabetically re-order properties and improve indentation. Signed-off-by: Marcel Ziswiler --- (no changes since v1) arch/arm/boot/dts/imx7-colibri.dtsi | 35 ++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index e20b0977f38f..074ebb0f8001 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -83,21 +83,34 @@ &ecspi3 { }; &fec1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_enet1>; - pinctrl-1 = <&pinctrl_enet1_sleep>; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; - clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; assigned-clock-rates = <0>, <100000000>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>; + fsl,magic-packet; + phy-handle = <ðphy0>; phy-mode = "rmii"; phy-supply = <®_LDO1>; - fsl,magic-packet; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-1 = <&pinctrl_enet1_sleep>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + micrel,led-mode = <0>; + reg = <0>; + }; + }; }; &flexcan1 {