| Message ID | 20220830165817.183571-5-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Accepted |
| Commit | ff8d92038cf92c886873c0e0628ba1272e6a087c |
| Headers | show |
| Series | Improvements to the Qcom PCIe Endpoint driver | expand |
On Sat, Sep 03, 2022 at 10:36:53AM +0800, kernel test robot wrote: > Hi Manivannan, > > I love your patch! Yet something to improve: > > [auto build test ERROR on robh/for-next] > [also build test ERROR on linus/master v6.0-rc3 next-20220901] > [cannot apply to helgaas-pci/next] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Manivannan-Sadhasivam/Improvements-to-the-Qcom-PCIe-Endpoint-driver/20220831-010315 > base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next > config: arm-allyesconfig (https://download.01.org/0day-ci/archive/20220903/202209031046.rOZKOVqT-lkp@intel.com/config) > compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0 > reproduce (this is a W=1 build): > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # https://github.com/intel-lab-lkp/linux/commit/dec4c93b2077408cecddd53950905bf2411019b0 > git remote add linux-review https://github.com/intel-lab-lkp/linux > git fetch --no-tags linux-review Manivannan-Sadhasivam/Improvements-to-the-Qcom-PCIe-Endpoint-driver/20220831-010315 > git checkout dec4c93b2077408cecddd53950905bf2411019b0 > # save the config file > mkdir build_dir && cp config build_dir/.config > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash > > If you fix the issue, kindly add following tag where applicable > Reported-by: kernel test robot <lkp@intel.com> > > All errors (new ones prefixed by >>): > > drivers/pci/controller/dwc/pcie-qcom-ep.c: In function 'qcom_pcie_ep_probe': > >> drivers/pci/controller/dwc/pcie-qcom-ep.c:672:21: error: 'struct dw_pcie' has no member named 'edma' > 672 | pcie_ep->pci.edma.nr_irqs = 1; This patch depends on the eDMA series from Sergey (Sorry, I forgot to mention this in cover letter): [PATCH RESEND v5 00/24] dmaengine: dw-edma: Add RP/EP local DMA controllers support But the eDMA series is still getting reviews and I don't hear any news about respin. So in the next revision I'm gonna drop this patch. Thanks, Mani > | ^ > > > vim +672 drivers/pci/controller/dwc/pcie-qcom-ep.c > > 658 > 659 static int qcom_pcie_ep_probe(struct platform_device *pdev) > 660 { > 661 struct device *dev = &pdev->dev; > 662 struct qcom_pcie_ep *pcie_ep; > 663 int ret; > 664 > 665 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); > 666 if (!pcie_ep) > 667 return -ENOMEM; > 668 > 669 pcie_ep->pci.dev = dev; > 670 pcie_ep->pci.ops = &pci_ops; > 671 pcie_ep->pci.ep.ops = &pci_ep_ops; > > 672 pcie_ep->pci.edma.nr_irqs = 1; > 673 platform_set_drvdata(pdev, pcie_ep); > 674 > 675 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); > 676 if (ret) > 677 return ret; > 678 > 679 ret = qcom_pcie_enable_resources(pcie_ep); > 680 if (ret) { > 681 dev_err(dev, "Failed to enable resources: %d\n", ret); > 682 return ret; > 683 } > 684 > 685 ret = dw_pcie_ep_init(&pcie_ep->pci.ep); > 686 if (ret) { > 687 dev_err(dev, "Failed to initialize endpoint: %d\n", ret); > 688 goto err_disable_resources; > 689 } > 690 > 691 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep); > 692 if (ret) > 693 goto err_disable_resources; > 694 > 695 return 0; > 696 > 697 err_disable_resources: > 698 qcom_pcie_disable_resources(pcie_ep); > 699 > 700 return ret; > 701 } > 702 > > -- > 0-DAY CI Kernel Test Service > https://01.org/lkp
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 1e09eca5b3b2..54b927adf60a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -66,6 +66,7 @@ #define PARF_INT_ALL_PLS_ERR BIT(15) #define PARF_INT_ALL_PME_LEGACY BIT(16) #define PARF_INT_ALL_PLS_PME BIT(17) +#define PARF_INT_ALL_EDMA BIT(22) /* PARF_BDF_TO_SID_CFG register fields */ #define PARF_BDF_TO_SID_BYPASS BIT(0) @@ -367,7 +368,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK); val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME | PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | - PARF_INT_ALL_LINK_UP; + PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA; writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep); @@ -670,6 +671,7 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) pcie_ep->pci.dev = dev; pcie_ep->pci.ops = &pci_ops; pcie_ep->pci.ep.ops = &pci_ep_ops; + pcie_ep->pci.edma.nr_irqs = 1; platform_set_drvdata(pdev, pcie_ep); ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);
Qualcomm PCIe Endpoint controllers have the in-built Embedded DMA (eDMA) peripheral for offloading the data transfer between PCIe bus and memory. Let's add the support for it by enabling the eDMA IRQ in the driver. Rest of the functionality will be handled by the eDMA DMA Engine driver. Since the eDMA on Qualcomm platforms only uses a single IRQ for all channels, use 1 for edma.nr_irqs. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)