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Niedermayr" To: , CC: , , , Subject: [PATCH v2 2/3] memory: omap-gpmc: add support for wait pin polarity Date: Mon, 5 Sep 2022 09:17:16 +0200 Message-ID: <20220905071717.1500568-3-benedikt.niedermayr@siemens.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220905071717.1500568-1-benedikt.niedermayr@siemens.com> References: <20220905071717.1500568-1-benedikt.niedermayr@siemens.com> MIME-Version: 1.0 X-Originating-IP: [139.21.146.182] X-ClientProxiedBy: DEMCHDC89XA.ad011.siemens.net (139.25.226.103) To DEMCHDC8A0A.ad011.siemens.net (139.25.226.106) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 542e8b72-86b6-43f9-c5d7-08da8f0eb1a9 X-MS-TrafficTypeDiagnostic: AM7PR10MB3779:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 24KxJ/BOfR9E+WcGs5JG1m6RItWxuMAbMlJC2t4SVmll4wIZo2BGG6JrikkWtrBl434YWbnZxO24cb2VbX7KixktrTUCikQpmi3fWDOCHR0rHKjB20zvcDZ/fu18NZMHYZ5Zp2qhPKW7THZxP6EkHMED8jyugpfcIttXXXrIiERvWCPpuvYP79MPUdo3fZlzsc6SQGrsTC1nDWdz5EPx40IMRoQPse3fEVH5HZWtePR8eE46wzcXbjh0LKUOqTI8KsCllE8u6HE3msAYym+Bdl1VCZiH+a9QMM3o4DmfhDQTSF+UQJaiGZQm6S7BO4oayhY10wiD/3toZnKoBqF66ZviPHnKObnny4HsrlxlPb4o66VABBYPC2qeEbG+7dW6R0wAxT1MoZxgYj6Ljde9DhE0enLeNRH3mSIp3LFCsZvKwImxHlrWeorUjZg4PhXvvNRiurZ9XkcyRK+9IcrVkl9lHDr8i+r65hJIP7RC2OVXO1nk9+XatV00yHm0+lwh81Ub0uRIX7kQpQOLDHJDXux/sz84JV29m5+l3lB2EYViQp0WdIf2VbkJLSqXAwXW7zqmpmfVktJ3HGRjqhZKp/Jh4q84+mly80UpZbrpw8xqDKw8l97iw/A62SHs9jdTo2b2Yk+gVwyzr8v+s9Cy1aQvmWwS2S1Oh4nmp8igARbczXeVqKie1CHgZFLYOtWY2bj8WEGsxlAjCzWmptydIm91Adapo9rOHV7ne07ztZvr1vuhF2eUprmFf0xsFMVSIXmkqZpp4C3Z31nM0PGQqQDf4BDgVWUH0/eJBPbtpwMeNNOIHnW/C/97ovJ/unfd X-Forefront-Antispam-Report: CIP:194.138.21.75; CTRY:DE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:hybrid.siemens.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(136003)(376002)(396003)(346002)(36840700001)(40470700004)(46966006)(4326008)(83380400001)(8676002)(16526019)(336012)(47076005)(70586007)(70206006)(36860700001)(8936002)(5660300002)(478600001)(26005)(6666004)(41300700001)(1076003)(186003)(2616005)(956004)(86362001)(316002)(54906003)(82310400005)(110136005)(40480700001)(40460700003)(36756003)(81166007)(82740400003)(2906002)(82960400001)(356005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: siemens.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2022 07:17:29.8416 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 542e8b72-86b6-43f9-c5d7-08da8f0eb1a9 X-MS-Exchange-CrossTenant-Id: 38ae3bcd-9579-4fd4-adda-b42e1495d55a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=38ae3bcd-9579-4fd4-adda-b42e1495d55a; Ip=[194.138.21.75]; Helo=[hybrid.siemens.com] X-MS-Exchange-CrossTenant-AuthSource: HE1EUR01FT091.eop-EUR01.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR10MB3779 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Benedikt Niedermayr Setting the wait pin polarity from the device tree is currently not possible. The device tree property "gpmc,wait-pin-polarity" can be used for that. If this property is missing the previous default value is used instead, which preserves backwards compatibility. The wait pin polarity is then set via the gpiochip direction_input callback function. Signed-off-by: Benedikt Niedermayr --- drivers/memory/omap-gpmc.c | 30 ++++++++++++++++++++----- include/linux/platform_data/gpmc-omap.h | 1 + 2 files changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c index 579903457415..be3c35ae9619 100644 --- a/drivers/memory/omap-gpmc.c +++ b/drivers/memory/omap-gpmc.c @@ -35,6 +35,8 @@ #include +#include "../gpio/gpiolib.h" + #define DEVICE_NAME "omap-gpmc" /* GPMC register offsets */ @@ -1980,6 +1982,11 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) "gpmc,wait-on-read"); p->wait_on_write = of_property_read_bool(np, "gpmc,wait-on-write"); + p->wait_pin_polarity = of_property_read_u32(np, + "gpmc,wait-pin-polarity", + &p->wait_pin_polarity); + if (p->wait_pin_polarity < 0) + p->wait_pin_polarity = GPIO_ACTIVE_HIGH; if (!p->wait_on_read && !p->wait_on_write) pr_debug("%s: rd/wr wait monitoring not enabled!\n", __func__); @@ -2210,10 +2217,11 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) { unsigned int wait_pin = gpmc_s.wait_pin; - waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip, - wait_pin, "WAITPIN", - GPIO_ACTIVE_HIGH, - GPIOD_IN); + waitpin_desc = + gpiochip_request_own_desc(&gpmc->gpio_chip, + wait_pin, "WAITPIN", + gpmc_s.wait_pin_polarity ? GPIO_ACTIVE_HIGH : GPIO_ACTIVE_LOW, + GPIOD_IN); if (IS_ERR(waitpin_desc)) { ret = PTR_ERR(waitpin_desc); if (ret == -EBUSY) { @@ -2342,7 +2350,19 @@ static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) static int gpmc_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { - return 0; /* we're input only */ + u32 reg; + struct gpio_desc *desc = gpiochip_get_desc(chip, offset); + + offset += 8; + reg = gpmc_read_reg(GPMC_CONFIG); + + if (BIT(FLAG_ACTIVE_LOW) & desc->flags) + reg &= ~BIT(offset); + else + reg |= BIT(offset); + + gpmc_write_reg(GPMC_CONFIG, reg); + return 0; } static int gpmc_gpio_direction_output(struct gpio_chip *chip, diff --git a/include/linux/platform_data/gpmc-omap.h b/include/linux/platform_data/gpmc-omap.h index c9cc4e32435d..bf4f2246f31d 100644 --- a/include/linux/platform_data/gpmc-omap.h +++ b/include/linux/platform_data/gpmc-omap.h @@ -149,6 +149,7 @@ struct gpmc_settings { u32 device_width; /* device bus width (8 or 16 bit) */ u32 mux_add_data; /* multiplex address & data */ u32 wait_pin; /* wait-pin to be used */ + u32 wait_pin_polarity; /* wait-pin polarity */ }; /* Data for each chip select */