From patchwork Fri Sep 9 13:53:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Martin_Povi=C5=A1er?= X-Patchwork-Id: 604342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CD0FC6FA86 for ; Fri, 9 Sep 2022 13:54:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229546AbiIINyv (ORCPT ); Fri, 9 Sep 2022 09:54:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230249AbiIINyp (ORCPT ); Fri, 9 Sep 2022 09:54:45 -0400 Received: from hutie.ust.cz (unknown [IPv6:2a03:3b40:fe:f0::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CE3D5FDD; Fri, 9 Sep 2022 06:54:39 -0700 (PDT) From: =?utf-8?q?Martin_Povi=C5=A1er?= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cutebit.org; s=mail; t=1662731677; bh=Z7pYWBxGHGi2ZqyTkPEZO2suk0cCsfJNF1GKYGMYE+w=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=YIrvjtlCimCjWTg2ae3mEonUuQy1i8q8nTG/UASHn9xFMpLmofoXtJV8M9onSKS48 UptY1jVASNQwNQ6t5KwTomsiqGd+LU/5OUfQyjfCqiI7v+ASWdZTTBiuTk03IZ/9xH 2wOEezk/qHdL/U+idErfiohqp9IecoqzfSklgT4Q= To: James Schulman , David Rhodes , Lucas Tanure , Richard Fitzgerald , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Jaroslav Kysela , Takashi Iwai , =?utf-8?q?Martin_Povi=C5=A1er?= Cc: Charles Keepax , ChiYuan Huang , Pierre-Louis Bossart , Lukas Bulwahn , Matt Flax , - , alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev Subject: [PATCH 02/10] ASoC: cs42l42: Add bitclock frequency argument to cs42l42_pll_config() Date: Fri, 9 Sep 2022 15:53:26 +0200 Message-Id: <20220909135334.98220-3-povik+lin@cutebit.org> In-Reply-To: <20220909135334.98220-1-povik+lin@cutebit.org> References: <20220909135334.98220-1-povik+lin@cutebit.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Richard Fitzgerald Clean up the handling of bitclock frequency by keeping all the logic in cs42l42_pcm_hw_params(), which then simply passes the frequency as an argument to cs42l42_pll_config(). The previous code had become clunky as a legacy of earlier versions of the clock handling. The logic was split across cs42l42_pcm_hw_params() and cs42l42_pll_config(), with the params-derived bclk stashed in struct cs42l42_private only to pass it to cs42l42_pll_config(). Signed-off-by: Richard Fitzgerald Signed-off-by: Martin PoviĊĦer --- sound/soc/codecs/cs42l42.c | 32 ++++++++++++++++---------------- sound/soc/codecs/cs42l42.h | 1 - 2 files changed, 16 insertions(+), 17 deletions(-) diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c index de1e276bdf7d..0048ce977645 100644 --- a/sound/soc/codecs/cs42l42.c +++ b/sound/soc/codecs/cs42l42.c @@ -647,18 +647,12 @@ static const struct cs42l42_pll_params pll_ratio_table[] = { { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1} }; -static int cs42l42_pll_config(struct snd_soc_component *component) +static int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk) { struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); int i; - u32 clk; u32 fsync; - if (!cs42l42->sclk) - clk = cs42l42->bclk; - else - clk = cs42l42->sclk; - /* Don't reconfigure if there is an audio stream running */ if (cs42l42->stream_use) { if (pll_ratio_table[cs42l42->pll_config].sclk == clk) @@ -895,19 +889,25 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, unsigned int width = (params_width(params) / 8) - 1; unsigned int slot_width = 0; unsigned int val = 0; + unsigned int bclk; int ret; cs42l42->srate = params_rate(params); - /* - * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being - * more than assumed (which would result in overclocking). - */ - if (params_width(params) == 24) - slot_width = 32; + if (cs42l42->sclk) { + /* machine driver has set the SCLK */ + bclk = cs42l42->sclk; + } else { + /* + * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being + * more than assumed (which would result in overclocking). + */ + if (params_width(params) == 24) + slot_width = 32; - /* I2S frame always has multiple of 2 channels */ - cs42l42->bclk = snd_soc_tdm_params_to_bclk(params, slot_width, 0, 2); + /* I2S frame always has multiple of 2 channels */ + bclk = snd_soc_tdm_params_to_bclk(params, slot_width, 0, 2); + } switch (substream->stream) { case SNDRV_PCM_STREAM_CAPTURE: @@ -947,7 +947,7 @@ static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, break; } - ret = cs42l42_pll_config(component); + ret = cs42l42_pll_config(component, bclk); if (ret) return ret; diff --git a/sound/soc/codecs/cs42l42.h b/sound/soc/codecs/cs42l42.h index 50299c9f283a..b4ba1467c558 100644 --- a/sound/soc/codecs/cs42l42.h +++ b/sound/soc/codecs/cs42l42.h @@ -30,7 +30,6 @@ struct cs42l42_private { struct snd_soc_jack *jack; struct mutex irq_lock; int pll_config; - int bclk; u32 sclk; u32 srate; u8 plug_state;