From patchwork Tue Sep 13 13:14:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 605462 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5C32C6FA90 for ; Tue, 13 Sep 2022 13:15:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232174AbiIMNPY (ORCPT ); Tue, 13 Sep 2022 09:15:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229876AbiIMNPP (ORCPT ); Tue, 13 Sep 2022 09:15:15 -0400 Received: from mail.kapsi.fi (mail.kapsi.fi [IPv6:2001:67c:1be8::25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D5D11147A; Tue, 13 Sep 2022 06:15:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kapsi.fi; s=20161220; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=p6QzHQt11OGlMmkTQfhRjLd3f6wmGLkJhnf488+Wpoc=; b=R5a8gg3mrVQ44eu8OqpBuaHekR eJoSsUZ6HZApkUs7BgpkCtrGP6F5iGwV1ZNsSg/26pNsoUAFzd+tmFdayHfJU8oUeN/NoBVvN3zo7 vtHNYmFEErBRcBhPqZFDMwqs73ofkinbGVSCpt7DTTa+q7y9SBUCUMayPRKwUjYUDU8SCZiWuSPLO mCmVN9WfI+Yvz9FLYJhs0D44CzpLwq80nHYF7q7L1TFnvie9m4nl0mSarvnMf3bhQjHbrfF4+OqiJ qtkjqOrFLrsPlNuAEZ2DXU0gMUGQz2TRbAxzTC9ia8B04gIFN1QgmndDbJG06rvz0l9cSUpRpR7O9 cQ5X6GTw==; Received: from 91-158-25-70.elisa-laajakaista.fi ([91.158.25.70] helo=toshino.localdomain) by mail.kapsi.fi with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oY5kh-00EVnM-6S; Tue, 13 Sep 2022 16:14:59 +0300 From: Mikko Perttunen To: Thierry Reding , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Jonathan Hunter Cc: Mikko Perttunen , Krzysztof Kozlowski , Ashish Mhetre , Sameer Pujar , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/8] dt-bindings: Add headers for NVDEC on Tegra234 Date: Tue, 13 Sep 2022 16:14:40 +0300 Message-Id: <20220913131447.2877280-3-cyndis@kapsi.fi> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220913131447.2877280-1-cyndis@kapsi.fi> References: <20220913131447.2877280-1-cyndis@kapsi.fi> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 91.158.25.70 X-SA-Exim-Mail-From: cyndis@kapsi.fi X-SA-Exim-Scanned: No (on mail.kapsi.fi); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Mikko Perttunen Add clock, memory controller, powergate and reset dt-binding headers necessary for NVDEC. Signed-off-by: Mikko Perttunen Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/tegra234-clock.h | 4 ++++ include/dt-bindings/memory/tegra234-mc.h | 3 +++ include/dt-bindings/power/tegra234-powergate.h | 1 + include/dt-bindings/reset/tegra234-reset.h | 1 + 4 files changed, 9 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 173364a93381..25b4a3fb4588 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -82,6 +82,8 @@ #define TEGRA234_CLK_I2S6 66U /** @brief clock recovered from I2S6 input */ #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ +#define TEGRA234_CLK_NVDEC 83U /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ #define TEGRA234_CLK_PLLA 93U /** @brief PLLP clk output */ @@ -130,6 +132,8 @@ #define TEGRA234_CLK_SYNC_I2S5 149U /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ #define TEGRA234_CLK_SYNC_I2S6 150U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */ +#define TEGRA234_CLK_TSEC_PKA 154U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ #define TEGRA234_CLK_UARTA 155U /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 62987b47ce81..75f0bd30d365 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -32,6 +32,7 @@ #define TEGRA234_SID_PCIE10 0x0b #define TEGRA234_SID_BPMP 0x10 #define TEGRA234_SID_HOST1X 0x27 +#define TEGRA234_SID_NVDEC 0x29 #define TEGRA234_SID_VIC 0x34 /* @@ -91,6 +92,8 @@ #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 #define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c #define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d +#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78 +#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79 /* BPMP read client */ #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 /* BPMP write client */ diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h index ae9286cef85c..e5dc1e00be95 100644 --- a/include/dt-bindings/power/tegra234-powergate.h +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -19,6 +19,7 @@ #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U #define TEGRA234_POWER_DOMAIN_MGBED 20U +#define TEGRA234_POWER_DOMAIN_NVDEC 23U #define TEGRA234_POWER_DOMAIN_VIC 29U #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index d48d22b2bc7f..17163019316c 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -30,6 +30,7 @@ #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_NVDEC 44U #define TEGRA234_RESET_MGBE0_PCS 45U #define TEGRA234_RESET_MGBE0_MAC 46U #define TEGRA234_RESET_MGBE1_PCS 49U