From patchwork Thu Sep 15 18:15:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 606634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F9D3C6FA89 for ; Thu, 15 Sep 2022 18:18:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230054AbiIOSSM (ORCPT ); Thu, 15 Sep 2022 14:18:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230051AbiIOSRx (ORCPT ); Thu, 15 Sep 2022 14:17:53 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0F8B9F76F; Thu, 15 Sep 2022 11:17:41 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id n10so1523776wrw.12; Thu, 15 Sep 2022 11:17:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=xzoqzDtndDkISsSwTujowyDPoGXKL8jqH4hdlXLXrA0=; b=g5ulsbtE6DartTUDwK1K53pxs737iOAFvah1Hi8jK5pmVKn8KAVEf6OvssWURbZdFo dOSWToLwlaQwdJ18U4d1RedSFWSgxN+7k0AN5OqBda/cevb25gOLuTuI4LLibl9keWto N4Q825SAEdoOvDk6rXAoR/pJs7twaguzQCwGvopOeL3C4STOtA0O7SZgrNRYy1wyTxRZ 9jvDY4BZL8Srqk7Y+0B8Gc61zSI9T8yYmC2DmzFDp33WvqFBWINF5x4NaI7ujWuZuoTk DlNo+uDiS/xJUShEyQUfQ0UwDltURs02MR4sa1gaqN6zbcRSatsrYEFTxBqxt7dBSZ4p ay3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=xzoqzDtndDkISsSwTujowyDPoGXKL8jqH4hdlXLXrA0=; b=GKPuEmJ7jarW93RFlCuEp4Zld5Gey5ggZ7KxLAa6TIbtdhOiW/nlpBAkpPR3KXeuwa ikgLrjHTwdm6dWMqC28pkOpbKUkN6gTA5yMnTUK6wZeXtyK0TdKTGSYighwWwb4N6pgX p8dOWf3ku1j306Hw1X7GYI0LsigOSSEfad9+DjpUj4ffoJV0Y9Mz1QTtgXCtB2bsSppe M8LNRWJQFDCFe+GAyyZ/fHhNyMWhPFwHjabDCf6Uu/RGnRrTNUf0d9od5kPg5hVlW/l+ FZPitbH0WhUZo8p0KWT7j7ixUux38BeANgcE09UWKBOV7Oe4S799XDfcK3DRLyb7FeSN 75uw== X-Gm-Message-State: ACrzQf3wvL0zA8XdiWNBUpuxUSnKOyPQzB2qJlbEuPV9eM6u6PUTuySL 072nAEl3CP8mKQO0SaIbGToOyezcXG8YJQ== X-Google-Smtp-Source: AMsMyM7tjqwmJxX5D4dBi01RrRk+6JKiqTi1egw5XeegPGl6fRnFXsEXlXXpxAL3CklC75qxxfrBMg== X-Received: by 2002:a05:6000:384:b0:22a:5d05:c562 with SMTP id u4-20020a056000038400b0022a5d05c562mr579729wrf.701.1663265861500; Thu, 15 Sep 2022 11:17:41 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:d411:a48b:4035:3d98]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b003b47e8a5d22sm4243151wmq.23.2022.09.15.11.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 11:17:40 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Heiko Stuebner , Atish Patra , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 10/10] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Date: Thu, 15 Sep 2022 19:15:58 +0100 Message-Id: <20220915181558.354737-11-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Enable Renesas RZ/Five SoC config in defconfig. It allows the default upstream kernel to boot on RZ/Five SMARC EVK board. Alongside enable SERIAL_SH_SCI config so that the serial driver used by RZ/Five SoC is built-in. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- v2->v3 * Included RB tags * Updated commit description v1->v2 * New patch --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 05fd5fcf24f9..3dd9aa4d707d 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -26,6 +26,7 @@ CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set CONFIG_PROFILING=y CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_SOC_RENESAS_RZFIVE=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_SOC_VIRT=y @@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SH_SCI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y