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Niedermayr" To: , CC: , , , Subject: [PATCH v5 1/3] memory: omap-gpmc: allow shared wait pins Date: Fri, 16 Sep 2022 14:07:47 +0200 Message-ID: <20220916120749.2517727-2-benedikt.niedermayr@siemens.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220916120749.2517727-1-benedikt.niedermayr@siemens.com> References: <20220916120749.2517727-1-benedikt.niedermayr@siemens.com> MIME-Version: 1.0 X-Originating-IP: [144.145.220.65] X-ClientProxiedBy: DEMCHDC89XA.ad011.siemens.net (139.25.226.103) To DEMCHDC89XA.ad011.siemens.net (139.25.226.103) X-TM-AS-Product-Ver: SMEX-14.0.0.3080-8.6.1018-26680.007 X-TM-AS-Result: No-10--12.932000-8.000000 X-TMASE-MatchedRID: YeslW8iZUfPMYa5soaxdevS8hmHHS12Le/GSmEODdnIdZEkR8Y/meX+s iCf/QKJTdANxGD2/8Th88Abx2XH5NlppNBoXxD2IjUkjodfNrfZjFNgY8SnxHA3BRWEgXqlWWNb BpQ++I1mRiV0eo0RbuK1uNfgQaqvvSqdra4WWujyPQi9XuOWoOEPu4/hW5W83U9ht8cPjV45nAs t8At+c3ceQfu6iwSfsJVibDTTQXq1wDPi4qgkFxCfEMauXqN9RTVAfo9STYMOK5Jq39CIIv+uLF ZZYlisfHxPMjOKY7A8LbigRnpKlKTpcQTtiHDgWM36TonZTaOPY8ftIlo0kbUqSpMkU30hB0m0/ /9UUQaRta2wryESZag== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--12.932000-8.000000 X-TMASE-Version: SMEX-14.0.0.3080-8.6.1018-26680.007 X-TM-SNTS-SMTP: AD166C68398BD1A34AA7112FCE0560E7EF40665841A8F99ACB28101A975A4D462000:8 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: HE1EUR01FT063:EE_|PAXPR10MB5638:EE_ X-MS-Office365-Filtering-Correlation-Id: 22677c36-62cf-4ce0-9dd4-08da97dc1ac7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uK62T+ymgefUu7GhCVsf/8SmjE0Nn23TtREA0AWv7ExuURTJt4e45psjDiAQ1O/Oosth0m+gDoNqzeMlzLoIDdqQZqY4NVMIVGEPaJUXlhFukoBI/CR7gslzfREGdDpoHTsP4KsBRbWnOaQlP+7mx77RLXIY0jl7yaLiufv6cn6EthHTbLBiwQpquwviElt0KNtJdtOdNN7el37VqFKJwdERAtu4nuzED5YUd5yeuc7iFCPi8+14oxDmh0eT0ActSegdCuEGau8TqTblf3ns8HAYkwnKGO6cuJ5EqxaGcXzHpgsIbbjJlvkPpg/oDkFByW7OCXm19h0FYDftiqTfZFAIQaFB2FsG4JfL2eKFtUZVNEYuZfMW7McZBll1xBz6L3oJb3mOllkDYQMcElqPUrX10+re+oVaUvANQFRytxqb2hXtjgw3LSh5qbXcPQ8gUzizmwfx5rU3i1Ulxf5cSeUFSDxYJ+vRdNg+awP4pEHOO39VgTv6hkzCY2joF3NtJd6oN0lckmAiK1sB/O1pYZZ5y73dGRuRr0G7OBjX4/Yf3/F3CkGXbLDsrH89FEoo3C2PbhhzVl5XuP64w3BpEqf17pW0/+F7bfycc+jqsO/hxBAeKyCj+Wqrc5WGecrhN5dRm2wehIb/Y0ikuszv2Fcc0KhtUJU4SwzudIkftYQkWK273vrQHod1CldYEE89KBoP26YrV68+FRMDa3o9saycXYWlBmx9x6KWpKcnGB3a9Y8h1NOkc598V9+bivw/VD+fsEtT8fXdGbrde7qHxw== X-Forefront-Antispam-Report: CIP:194.138.21.74; CTRY:DE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:hybrid.siemens.com; PTR:hybrid.siemens.com; CAT:NONE; SFS:(13230022)(4636009)(396003)(39860400002)(346002)(136003)(376002)(451199015)(40470700004)(36840700001)(46966006)(478600001)(110136005)(36860700001)(82740400003)(40480700001)(316002)(4326008)(70586007)(82310400005)(7596003)(356005)(26005)(7636003)(54906003)(8936002)(5660300002)(70206006)(40460700003)(2616005)(82960400001)(6666004)(8676002)(41300700001)(16526019)(2906002)(336012)(186003)(47076005)(86362001)(956004)(83380400001)(36756003)(1076003); DIR:OUT; SFP:1101; X-OriginatorOrg: siemens.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2022 12:08:02.3298 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22677c36-62cf-4ce0-9dd4-08da97dc1ac7 X-MS-Exchange-CrossTenant-Id: 38ae3bcd-9579-4fd4-adda-b42e1495d55a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=38ae3bcd-9579-4fd4-adda-b42e1495d55a; Ip=[194.138.21.74]; Helo=[hybrid.siemens.com] X-MS-Exchange-CrossTenant-AuthSource: HE1EUR01FT063.eop-EUR01.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR10MB5638 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Benedikt Niedermayr Newer kernels refuse to probe when using the same wait pin for different chipselect regions. But this may be a usecase when connecting for example FPGA or ASIC modules to the gpmc, which only got one wait pin installed. The wait-pin allocation is now tracked by the gpmc driver in order to be sure that the wait pin has been indeed requested by gpmc. Therefore the "wait_pin_alloc_mask" has been introduced. Signed-off-by: Benedikt Niedermayr --- drivers/memory/omap-gpmc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c index d9bf1c2ac319..ea495e93766b 100644 --- a/drivers/memory/omap-gpmc.c +++ b/drivers/memory/omap-gpmc.c @@ -232,6 +232,7 @@ struct gpmc_device { int irq; struct irq_chip irq_chip; struct gpio_chip gpio_chip; + unsigned long wait_pin_alloc_mask; int nirqs; struct resource *data; }; @@ -2221,9 +2222,16 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, GPIO_ACTIVE_HIGH, GPIOD_IN); if (IS_ERR(waitpin_desc)) { - dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin); ret = PTR_ERR(waitpin_desc); - goto err; + if (ret == -EBUSY && + test_bit(wait_pin, &gpmc->wait_pin_alloc_mask)) { + dev_info(&pdev->dev, "shared wait-pin: %d\n", wait_pin); + } else { + dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin); + goto err; + } + } else { + set_bit(wait_pin, &gpmc->wait_pin_alloc_mask); } }