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Wed, 19 Oct 2022 07:46:46 -0700 Received: from xhdbharatku40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.31 via Frontend Transport; Wed, 19 Oct 2022 09:46:44 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , Thippeswamy Havalige Subject: [PATCH 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge Date: Wed, 19 Oct 2022 20:16:39 +0530 Message-ID: <20221019144640.9458-1-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EE:EE_|DS7PR12MB5791:EE_ X-MS-Office365-Filtering-Correlation-Id: ab0b71b1-31b4-40e1-3b82-08dab1e0c019 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RBsqyhwK8J9mmkzXugHk0OfgPmYxhQQPwSv38Rl1uo6KnYfgFr4JNMS5luUeEtJ2a/xgxzx1AsOAL0XelnKTYeA3O5CSeNb4mttOlbfGjHe95il4pXVD+cqj4UAceW8c2mlgcyyqgIg4pXRkmZilOE6PTwyYCa0iCoGYzIciRSjKoNlPw5dit3WEql6NDJ1sOXbd20slKyZ1P4Tv2rvaJzECElmsM9Sv8yW8osiqqevN5UnvWz9LYed8uO9XkQ9l7X3Owq6GKA8e30N0GnM8MvolYkY3Tmnc7HWJ49ixiowoVTsN36cDMH3RRt2mY9aERo6rG1kTkEqDBFaDIf4VBvbOaiTbvkf1ZFUtovxJXs23XKFgaEUEfd1ibj1qNruD4+bmYUe4YH6XKLk+jtp3dnWUPMHAM1XMEJnEmT771CSWxPuUvsVU4QOR8dqR26lrePnDs18P53Pi1Q05swfWzChZjgsEij1LsbGo64l5zXVjmJHtgyq7JEBMKrDECNMYoy0N8+8UXomJ1596SksteexbqVGSLWscZ7YhKiFKE3dRwa1/ywic02wgSia+2JdpieGmdlxf54nd07JiNalDqOPbFyh/x870/iojR3CLUHMAeZvv0wqSJuGn7dxHllNtdw794/teSeiAVkPaE4xOXWAMdQWpwKvLtwJzhiKHWkcqeIvrWwnVbbaehd2Kl+0cQr9SBFQIwWtqRN4ZlJ/9DxT8vUe43IsqxeBSagUkoa2Mdmad3GPQK4r62KWUd/cu1l7Wuj4w5VMKjUFk/QbE33S8wi/0gJtL2kiKRaXG+UHEHMi/tki2GVbJ8y2I8sjKUqy94GO3qgvjNP3UtmXhVz0lEq4Qh6HsiM0x5PiVgcBnl3wI08yBhuY63+swnHQX X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Signed-off-by: Thippeswamy Havalige --- .../devicetree/bindings/pci/xilinx-pcie.txt | 88 ------------------- .../devicetree/bindings/pci/xilinx-pcie.yaml | 81 +++++++++++++++++ 2 files changed, 81 insertions(+), 88 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt deleted file mode 100644 index fd57a81180a4..000000000000 --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt +++ /dev/null @@ -1,88 +0,0 @@ -* Xilinx AXI PCIe Root Port Bridge DT description - -Required properties: -- #address-cells: Address representation for root ports, set to <3> -- #size-cells: Size representation for root ports, set to <2> -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" -- reg: Should contain AXI PCIe registers location and length -- device_type: must be "pci" -- interrupts: Should contain AXI PCIe interrupt -- interrupt-map-mask, - interrupt-map: standard PCI properties to define the mapping of the - PCI interface to interrupt numbers. -- ranges: ranges for the PCI memory regions (I/O space region is not - supported by hardware) - Please refer to the standard PCI bus binding document for a more - detailed explanation - -Optional properties for Zynq/Microblaze: -- bus-range: PCI bus numbers covered - -Interrupt controller child node -+++++++++++++++++++++++++++++++ -Required properties: -- interrupt-controller: identifies the node as an interrupt controller -- #address-cells: specifies the number of cells needed to encode an - address. The value must be 0. -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. - -NOTE: -The core provides a single interrupt for both INTx/MSI messages. So, -created a interrupt controller node to support 'interrupt-map' DT -functionality. The driver will create an IRQ domain for this map, decode -the four INTx interrupts in ISR and route them to this domain. - - -Example: -++++++++ -Zynq: - pci_express: axi-pcie@50000000 { - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = < 0x50000000 0x1000000 >; - device_type = "pci"; - interrupts = < 0 52 4 >; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 1>, - <0 0 0 2 &pcie_intc 2>, - <0 0 0 3 &pcie_intc 3>, - <0 0 0 4 &pcie_intc 4>; - ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >; - - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - -Microblaze: - pci_express: axi-pcie@10000000 { - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = <0x10000000 0x4000000>; - device_type = "pci"; - interrupt-parent = <µblaze_0_intc>; - interrupts = <1 2>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 1>, - <0 0 0 2 &pcie_intc 2>, - <0 0 0 3 &pcie_intc 3>, - <0 0 0 4 &pcie_intc 4>; - ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>; - - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - - }; diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml b/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml new file mode 100644 index 000000000000..6b372ac1763e --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/xilinx-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx AXI PCIe Root Port Bridge DT description + +maintainers: + - Thippeswamy Havalige + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: xlnx,axi-pcie-host-1.00.a + + reg: + items: + - description: should contain AXI PCIe registers location and length + + interrupts: + items: + - description: should contain AXI PCIe interrupt + + ranges: + items: + - description: | + ranges for the PCI memory regions (I/O space region is not + supported by hardware) + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: identifies the node as an interrupt controller + type: object + properties: + "interrupt-controller": true + "#address-cells": + const: 0 + "#interrupt-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - ranges + - device_type + - interrupt-map + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + - | + + Zynq: + pci_express: pcie@50000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "xlnx,axi-pcie-host-1.00.a"; + reg = < 0x50000000 0x1000000 >; + device_type = "pci"; + interrupts = < 0 52 4 >; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 1>, + <0 0 0 2 &pcie_intc 2>, + <0 0 0 3 &pcie_intc 3>, + <0 0 0 4 &pcie_intc 4>; + ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >; + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + };