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Tue, 25 Oct 2022 01:54:05 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , "Thippeswamy Havalige" Subject: [PATCH 12/13] microblaze/PCI: Remove support for Xilinx PCI host bridge Date: Tue, 25 Oct 2022 12:22:13 +0530 Message-ID: <20221025065214.4663-13-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221025065214.4663-1-thippeswamy.havalige@amd.com> References: <20221025065214.4663-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT040:EE_|IA0PR12MB7776:EE_ X-MS-Office365-Filtering-Correlation-Id: a47f1b61-5d91-40df-a81d-08dab655b76a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kqHu0DFl6j+xHnqgMfMgaBnNspr7fy2AspCxllqB97t/aTO7+n7cH2yAoqOJ+vDc2GmXinUtbg0udpsTuz7S5ob41bPAOXNyQeY1b1EEoaMu3dKvkyNLxCmX2IgxgoygrXyI86cRaqyN/zPbo6PrcOhDabaQV8udOwuZr5vq7YYO2TGcRxyTxwOoGT8qlmI/3N3xgkMNkw6ujEcaHXl3ey62Hci251ciyeV5CIYZxbgreBq3jS0zCCPxRxiXWp08NL9/VvX3q1xsNLPYwJ4r03vHKLRZ3EqaExgRQrje72x8V9aGYcKYFWIusZUx159qtSc+CaImQ4ObYbB4YPHlnIvHU2UdXubqJFQDfcV0F8A2Tyz6GhjEvFy6rBMgwflf4kLGauaHhv5nYxJcfMeFNtbEjJ0zmlE1HV6/FHxJpq6XKgsK6ONp0RB/sZVUqWFsepWGzWOZIk5mrKD/m6N7wpiLJb2NqetQRbdM3KizyTXWavzm2YIHJWeJhlBRyz/I9FjRIDI2t6we8mSUYz3aHHqmaCaryvevY/qahB/XzR4VC3tnyCk2qw7zVUCqdATiv0j44xVsYEGpKkR7uPrRfAR1KStekiUEBxlao5sOMtk/WtSoAkGZnOv3sBpGBG8orOdxPZplijwX7hrW/HeKJZsECYtsn4Bl14haF9SkWh08TPvX0DJcu/QDS2jfHj3atybsMuOv4svyQ28xXh68aaRANNJYjASueP6TGSaY/4HTT5gDBp3AJmmWKj7fU9ZpQef54bsfPS67Ubfowcpxmo/j7Juo4H9GVzrtGUSmm0pTYv66gm6p6CD7mSlZEMCC X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Signed-off-by: Thippeswamy Havalige --- arch/microblaze/Kconfig | 8 --- arch/microblaze/include/asm/pci-bridge.h | 6 -- arch/microblaze/include/asm/pci.h | 5 -- arch/microblaze/pci/Makefile | 1 - arch/microblaze/pci/xilinx_pci.c | 105 ------------------------------- 5 files changed, 125 deletions(-) delete mode 100644 arch/microblaze/pci/xilinx_pci.c diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 996132a..9bacdab 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -205,11 +205,3 @@ config TASK_SIZE default "0x80000000" endmenu - -menu "Bus Options" - -config PCI_XILINX - bool "Xilinx PCI host bridge support" - depends on PCI - -endmenu diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h index 5db2c66..be5f504 100644 --- a/arch/microblaze/include/asm/pci-bridge.h +++ b/arch/microblaze/include/asm/pci-bridge.h @@ -25,7 +25,6 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address) */ struct pci_controller { struct pci_bus *bus; - struct device_node *dn; struct list_head list_node; void __iomem *io_base_virt; @@ -37,11 +36,6 @@ struct pci_controller { }; #ifdef CONFIG_PCI -static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) -{ - return bus->sysdata; -} - static inline int isa_vaddr_is_ioport(void __iomem *address) { /* No specific ISA handling on ppc32 at this stage, it diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h index a75bf3b..91f1f71 100644 --- a/arch/microblaze/include/asm/pci.h +++ b/arch/microblaze/include/asm/pci.h @@ -38,12 +38,7 @@ struct file; -/* This part of code was originally in xilinx-pci.h */ -#ifdef CONFIG_PCI_XILINX -extern void __init xilinx_pci_init(void); -#else static inline void __init xilinx_pci_init(void) { return; } -#endif #endif /* __KERNEL__ */ #endif /* __ASM_MICROBLAZE_PCI_H */ diff --git a/arch/microblaze/pci/Makefile b/arch/microblaze/pci/Makefile index 3cbdf25..293b416 100644 --- a/arch/microblaze/pci/Makefile +++ b/arch/microblaze/pci/Makefile @@ -4,4 +4,3 @@ # obj-$(CONFIG_PCI) += pci-common.o iomap.o -obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c deleted file mode 100644 index 5dc4182..0000000 --- a/arch/microblaze/pci/xilinx_pci.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * PCI support for Xilinx plbv46_pci soft-core which can be used on - * Xilinx Virtex ML410 / ML510 boards. - * - * Copyright 2009 Roderick Colenbrander - * Copyright 2009 Secret Lab Technologies Ltd. - * - * The pci bridge fixup code was copied from ppc4xx_pci.c and was written - * by Benjamin Herrenschmidt. - * Copyright 2007 Ben. Herrenschmidt , IBM Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include -#include - -#define XPLB_PCI_ADDR 0x10c -#define XPLB_PCI_DATA 0x110 -#define XPLB_PCI_BUS 0x114 - -#define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \ - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY) - -static const struct of_device_id xilinx_pci_match[] = { - { .compatible = "xlnx,plbv46-pci-1.03.a", }, - {} -}; - -/** - * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration. - */ -static void xilinx_pci_fixup_bridge(struct pci_dev *dev) -{ - struct pci_controller *hose; - int i; - - if (dev->devfn || dev->bus->self) - return; - - hose = pci_bus_to_host(dev->bus); - if (!hose) - return; - - if (!of_match_node(xilinx_pci_match, hose->dn)) - return; - - /* Hide the PCI host BARs from the kernel as their content doesn't - * fit well in the resource management - */ - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; - } - - dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n", - pci_name(dev)); -} -DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge); - -#ifdef DEBUG -/** - * xilinx_pci_exclude_device - Don't do config access for non-root bus - * - * This is a hack. Config access to any bus other than bus 0 does not - * currently work on the ML510 so we prevent it here. - */ -static int -xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn) -{ - return (bus != 0); -} -#endif - -/** - * xilinx_pci_init - Find and register a Xilinx PCI host bridge - */ -void __init xilinx_pci_init(void) -{ - struct resource r; - void __iomem *pci_reg; - struct device_node *pci_node; - - pci_node = of_find_matching_node(NULL, xilinx_pci_match); - if (!pci_node) - return; - - if (of_address_to_resource(pci_node, 0, &r)) { - pr_err("xilinx-pci: cannot resolve base address\n"); - return; - } - - /* Set the max bus number to 255, and bus/subbus no's to 0 */ - pci_reg = of_iomap(pci_node, 0); - WARN_ON(!pci_reg); - out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff); - iounmap(pci_reg); - -}