| Message ID | 20221130200950.144618-11-a39.skl@gmail.com |
|---|---|
| State | Accepted |
| Commit | 323647d32e83fae7f1a81b40e12ca6b0b63e880c |
| Headers | show |
| Series | SM6115 DTS changes | expand |
On 30.11.2022 21:09, Adam Skladowski wrote: > Add I2C/SPI nodes for SM6115. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm6115.dtsi | 290 +++++++++++++++++++++++++++ > 1 file changed, 290 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi > index b30a5485671d..e676b9d117e3 100644 > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi > @@ -6,6 +6,7 @@ > #include <dt-bindings/clock/qcom,gcc-sm6115.h> > #include <dt-bindings/clock/qcom,sm6115-dispcc.h> > #include <dt-bindings/clock/qcom,rpmcc.h> > +#include <dt-bindings/dma/qcom-gpi.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/power/qcom-rpmpd.h> > @@ -365,6 +366,90 @@ tlmm: pinctrl@500000 { > interrupt-controller; > #interrupt-cells = <2>; > > + qup_i2c0_default: qup-i2c0-default-state { > + pins = "gpio0", "gpio1"; > + function = "qup0"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c1_default: qup-i2c1-default-state { > + pins = "gpio4", "gpio5"; > + function = "qup1"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c2_default: qup-i2c2-default-state { > + pins = "gpio6", "gpio7"; > + function = "qup2"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c3_default: qup-i2c3-default-state { > + pins = "gpio8", "gpio9"; > + function = "qup3"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c4_default: qup-i2c4-default-state { > + pins = "gpio12", "gpio13"; > + function = "qup4"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c5_default: qup-i2c5-default-state { > + pins = "gpio14", "gpio15"; > + function = "qup5"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi0_default: qup-spi0-default-state { > + pins = "gpio0", "gpio1","gpio2", "gpio3"; > + function = "qup0"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi1_default: qup-spi1-default-state { > + pins = "gpio4", "gpio5", "gpio69", "gpio70"; > + function = "qup1"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi2_default: qup-spi2-default-state { > + pins = "gpio6", "gpio7", "gpio71", "gpio80"; > + function = "qup2"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi3_default: qup-spi3-default-state { > + pins = "gpio8", "gpio9", "gpio10", "gpio11"; > + function = "qup3"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi4_default: qup-spi4-default-state { > + pins = "gpio12", "gpio13", "gpio96", "gpio97"; > + function = "qup4"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi5_default: qup-spi5-default-state { > + pins = "gpio14", "gpio15", "gpio16", "gpio17"; > + function = "qup5"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > sdc1_state_on: sdc1-on-state { > clk-pins { > pins = "sdc1_clk"; > @@ -701,6 +786,211 @@ gpi_dma0: dma-controller@4a00000 { > status = "disabled"; > }; > > + qupv3_id_0: geniqup@4ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x04ac0000 0x2000>; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + #address-cells = <1>; > + #size-cells = <1>; > + iommus = <&apps_smmu 0xe3 0x0>; > + ranges; > + status = "disabled"; > + > + i2c0: i2c@4a80000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x04a80000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c0_default>; > + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, > + <&gpi_dma0 1 0 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi0: spi@4a80000 { > + compatible = "qcom,geni-spi"; > + reg = <0x04a80000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi0_default>; > + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, > + <&gpi_dma0 1 0 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c1: i2c@4a84000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x04a84000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c1_default>; > + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, > + <&gpi_dma0 1 1 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi1: spi@4a84000 { > + compatible = "qcom,geni-spi"; > + reg = <0x04a84000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi1_default>; > + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, > + <&gpi_dma0 1 1 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c2: i2c@4a88000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x04a88000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c2_default>; > + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, > + <&gpi_dma0 1 2 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi2: spi@4a88000 { > + compatible = "qcom,geni-spi"; > + reg = <0x04a88000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi2_default>; > + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, > + <&gpi_dma0 1 2 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c3: i2c@4a8c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x04a8c000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c3_default>; > + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, > + <&gpi_dma0 1 3 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi3: spi@4a8c000 { > + compatible = "qcom,geni-spi"; > + reg = <0x04a8c000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi3_default>; > + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, > + <&gpi_dma0 1 3 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c4: i2c@4a90000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x04a90000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c4_default>; > + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, > + <&gpi_dma0 1 4 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi4: spi@4a90000 { > + compatible = "qcom,geni-spi"; > + reg = <0x04a90000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi4_default>; > + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, > + <&gpi_dma0 1 4 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c5: i2c@4a94000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x04a94000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c5_default>; > + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, > + <&gpi_dma0 1 5 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi5: spi@4a94000 { > + compatible = "qcom,geni-spi"; > + reg = <0x04a94000 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi5_default>; > + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, > + <&gpi_dma0 1 5 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + }; > + > usb_1: usb@4ef8800 { > compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; > reg = <0x04ef8800 0x400>;
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index b30a5485671d..e676b9d117e3 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,gcc-sm6115.h> #include <dt-bindings/clock/qcom,sm6115-dispcc.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -365,6 +366,90 @@ tlmm: pinctrl@500000 { interrupt-controller; #interrupt-cells = <2>; + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio4", "gpio5"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio8", "gpio9"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio12", "gpio13"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio14", "gpio15"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1","gpio2", "gpio3"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi1_default: qup-spi1-default-state { + pins = "gpio4", "gpio5", "gpio69", "gpio70"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi2_default: qup-spi2-default-state { + pins = "gpio6", "gpio7", "gpio71", "gpio80"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi3_default: qup-spi3-default-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi4_default: qup-spi4-default-state { + pins = "gpio12", "gpio13", "gpio96", "gpio97"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi5_default: qup-spi5-default-state { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -701,6 +786,211 @@ gpi_dma0: dma-controller@4a00000 { status = "disabled"; }; + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x04ac0000 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <1>; + #size-cells = <1>; + iommus = <&apps_smmu 0xe3 0x0>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a80000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x04a80000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x04a84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_default>; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x04a88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_default>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a8c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_default>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@4a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x04a8c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_default>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@4a90000 { + compatible = "qcom,geni-spi"; + reg = <0x04a90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_default>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a94000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_default>; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@4a94000 { + compatible = "qcom,geni-spi"; + reg = <0x04a94000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_default>; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; reg = <0x04ef8800 0x400>;
Add I2C/SPI nodes for SM6115. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 290 +++++++++++++++++++++++++++ 1 file changed, 290 insertions(+)